I take your advise SRAM and GAL makes a good ground for the design.
I wish to start with an updated GAL equations based on Brane's guidance,
It is commented I hope you can follow.
Code: Select all
GAL16V8
Glue logic for 512x8 SRAM
Sinclair QL RAM Expansion
(c)2014 Sinclair QL forum
# control bits set by assembler
# SYN = 1
# AC0 = 1
# AC1(n) = 1,1,1,1,1,1,1,1
#1 2 3 4 5 6 7 8 9 10
1 NC A19 A18 NC /DS NC NC NC GND
0 NC /RAMCE VALID NC /DTACK DSMCL NC NC VCC
#11 12 13 14 15 16 17 18 19 20
# input 1 is wired to VCC
# input 0 is wired to GND
# NC - signal not connected
# / - signal active on low level
# / NOT, + OR, * AND operators
# enables SRAM on VALID memory range and data strobe DS
VALID = A19 * /A18 + /A19 * A18
RAMCE = VALID * DS
# start of our cycle DSMCL goes high, else tristate high impedance
IF( VALID )
DSMCL = 1
# end of our cycle DTACK goes high, else tristate high impedance
IF( VALID * DS )
DTACK = 1
# END