janbredenbeek wrote: ↑Fri Dec 29, 2023 12:06 am
I just read that SMSQ/E attempts to emulate it but I don't know if that's limited to only the BEEP command or the IPC trap as well
It works even with games like Spook or Cuthbert, Tony Tebby implemented it for Q40/Q60 and I think he did quite a good job.
From the source I gather that the smsq.hdop trap is indeed implemented for QL sound, so it should work from machine code too.
(I have never used the Q68's sound output and actually sacrificed it for QLNET...).
Shame on you... and on me for not making QLNET part of the PCB... but interesting mod.
How did you do that? Remove the series capacitor for the sound output and solder the QLNET line there?
Yes, and this was not easy given the small space. I hope it can be undone now that I don't need QLNET anymore since I have QIMSI now...
janbredenbeek wrote: ↑Fri Dec 29, 2023 11:57 am
Yes, and this was not easy given the small space. I hope it can be undone now that I don't need QLNET anymore since I have QIMSI now...
Good luck. How does QIMSI replace QLNET for you? By SERNET?
Peter wrote: ↑Fri Jan 12, 2024 9:57 am
Good luck. How does QIMSI replace QLNET for you? By SERNET?
Yes, with the new Minerva SER driver I get about 8Kbytes/second when sending from QIMSI to Q68. The other way round is slower but works when I lower the baud rate to 57600.
(BTW, I have been in a long conversation with Mark Swift about the 'freeze' problems with firmware 1.05 and keyboard interrupts. Up to now still not resolved. See https://github.com/janbredenbeek/Minerva4Q68/issues/1 ).
Derek_Stewart wrote: ↑Fri Jan 12, 2024 2:39 pm
I am interested to know why QLNET and Sound can not be used together on a Q68, seems to both work at the same time for me.
Technically no problem, but I didn't want to drill an extra hole into the case for the extra jack and I didn't use the sound feature anyway, at that time.
No time to have a closer look at the moment, but Martyn made me aware of an other issue with FPGA version 1.05. It turned out that one was caused by synthesizing the FPGA logic under Windows 10. I rebuilt 1.05 version under Windows XP, which fixed it. Do you have a Lattice programmer to try?
No time to have a closer look at the moment, but Martyn made me aware of an other issue with FPGA version 1.05. It turned out that one was caused by synthesizing the FPGA logic under Windows 10. I rebuilt 1.05 version under Windows XP, which fixed it. Do you have a Lattice programmer to try?
Don't have, but my firmware version is still 1.00.
But there have been reports in this forum about the same problem (Dilwyn?). Maybe someone with a programmer can test this?
Derek_Stewart wrote: ↑Sun Jan 14, 2024 5:27 pm
The last batch of Q68, Batch 4, has the Q68 FPGA code programmed to v1.05, which us the new recreated code.
I'm on v1.05, how do I check if I have an affected system?
What are the symptoms?
Mark Swift wrote: ↑Tue Jan 16, 2024 7:43 am
I'm on v1.05, how do I check if I have an affected system?
What are the symptoms?
They surfaced when Martyn tests his QLNET driver. Unfortunately they are so rare that I can not even reproduce them myself.
I can't say if there is a connection to your problem or not - I simply have no time to dig into https://github.com/janbredenbeek/Minerva4Q68/issues/1 at this time.
Maybe Derek can find out by the delivery date whether your board is affected?
