The Sinclair QL Forum

Ok, so if I am right that only pins 13 to 18 need to be checked to find out if they are output or input, then this is what I have:

Pin
13 - Goes to the base of a BC238B Transistor (so is an Output).
14 - Goes to the EXTINT connection on the expansion slot connector (so is an Output).
15 - Goes to pin 18 of a 74LS244, which is an output on the 74LS244 (so is an Input).
16 - Goes to pin 19 of the same 74LS244, which is 'enable' (so is an Output).
17 - Goes to pin 9 of a 74HCT164, which is 'clear' (so is an Output).
18 - Goes to pin 20 of the 27128 EPROM, which is 'enable' (so is an Output).

Does that all look correct?

I don't know if that is correct. Sorry

Instead of a text description, maybe you need to create a schematic?

I think it was :S

So I generated a .PDS file, following the instructions here (p210 onwards):

https://8bit-museum.de/download/chiptes ... ro_1.2.pdf

Then using PALASM I eventually generated a .JED file.

I had issues generating as PALASM presented an error: Signal IO19 cannot have more than 8 product term(s). I modified the .PDS, burnt the result to a GAL16V8, but it didn't work (QL boots with black screen, doesn't get any further).

I've attached a zip that contains the unmodified .PDS (that failed in PALASM due to more than 8 product terms for IO19), the .PDS that I modified (probably incorrectly - I shortened io19 as it was very similar to io13!) and the .JED file generated from the modified .PDS.

I'll leave that here in case anyone ever stumbles upon it or in case it's useful in the right hands, and will give up for now!