SMSQE in MisTer
Posted: Sun Oct 03, 2021 12:07 pm
I am interested in Marcel Kilgus's SMSQ/E on MiSTer project but his webpage does not make it clear (to me) what one has to buy/do to build it. What is the maximum display resolution of his design and does it use HDMI for output?
I see that the FX68K core is written in SystemVerilog does that imply that the rest of the design is also written in SV?
Is the system portable, ie. can it run in any fpga large enough to accommodate it or is it dependent on the MiSTer hardware?
I recorded Marcel's recent talk on m68k including the after-talk Q&A but I stopped the recording just as he mentioned his FPGA skills, which he claimed were limited. SMSQ/E in FPGA is a remarkable achievement for someone with limited skills!
I "Googled" MiSTer and found that it is based on Terasic DE10-Nano Altera/Intel Cyclone V SoC experimenter's board which, strangely, is cheaper to buy (76 pounds) here in Switzerland than directly from Terasic.
From GitHub:-
MiSTer utilizes a readily available FPGA board called the 'DE10-Nano', which connects to your TV or monitor via HDMI video out. It can additionally be expanded with various add-ons (such as a USB hub, SDRAM, audio and VGA out).
The MiSTer software/OS itself is freely downloadable, and anyone is welcome to contribute to its development. In fact MiSTer relies on the contributions of many developers for the various systems (known as 'cores') it replicates.
and
FX68K 68000 cycle accurate SystemVerilog core Copyright (c) 2018 by Jorge Cwik fx68k@fxatari.com
FX68K is a 68000 cycle exact compatible core. At least in theory, it should be impossible to distinguish functionally from a real 68K processor.
On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max effective clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance.
The core is fully synchronous. Considerable effort was made to avoid any asynchronous logic.
Written in SystemVerilog.
The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal.
It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented.
I also found the following info on the Internoodle (as a friend of mine calls it)
https://www.theverge.com/22323002/miste ... e-early-pc
https://www.terasic.com.tw/cgi-bin/page ... 67&No=1046
I see that the FX68K core is written in SystemVerilog does that imply that the rest of the design is also written in SV?
Is the system portable, ie. can it run in any fpga large enough to accommodate it or is it dependent on the MiSTer hardware?
I recorded Marcel's recent talk on m68k including the after-talk Q&A but I stopped the recording just as he mentioned his FPGA skills, which he claimed were limited. SMSQ/E in FPGA is a remarkable achievement for someone with limited skills!
I "Googled" MiSTer and found that it is based on Terasic DE10-Nano Altera/Intel Cyclone V SoC experimenter's board which, strangely, is cheaper to buy (76 pounds) here in Switzerland than directly from Terasic.
From GitHub:-
MiSTer utilizes a readily available FPGA board called the 'DE10-Nano', which connects to your TV or monitor via HDMI video out. It can additionally be expanded with various add-ons (such as a USB hub, SDRAM, audio and VGA out).
The MiSTer software/OS itself is freely downloadable, and anyone is welcome to contribute to its development. In fact MiSTer relies on the contributions of many developers for the various systems (known as 'cores') it replicates.
and
FX68K 68000 cycle accurate SystemVerilog core Copyright (c) 2018 by Jorge Cwik fx68k@fxatari.com
FX68K is a 68000 cycle exact compatible core. At least in theory, it should be impossible to distinguish functionally from a real 68K processor.
On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max effective clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance.
The core is fully synchronous. Considerable effort was made to avoid any asynchronous logic.
Written in SystemVerilog.
The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal.
It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented.
I also found the following info on the Internoodle (as a friend of mine calls it)
https://www.theverge.com/22323002/miste ... e-early-pc
https://www.terasic.com.tw/cgi-bin/page ... 67&No=1046