74HCxx vs 74LSxx

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Nasta
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Re: 74HCxx vs 74LSxx

Postby Nasta » Tue Aug 13, 2019 12:11 pm

Interesting that no-one mentioned the biggest difference between HC and LS - power requirements. HC(T) uses power practically only when the signal transitions or there is a resistive load, the latter not being the case when it only drives other HC(T) or CMOS and indeed NMOS circuits like CPU or FPU pins. In these conditions, changing LS with HC(T) is almost like getting the same curcuit just without the power drain of the LS chip you just replaced - it can be quite dramatic.

Also, as to the circuit design in question - HCT should be used at least for the 08 ans 27 chips, not HC. HC could be used safely only it the CPU is a HC or EC variant. The reason for this is the CPU, despite being a MOS device, has TTL compatible output levels when the pins are loaded, which means, depending on the load on the particular signal, the high level might fall below what HC recognizes as a high level (2/3 of it's power supply voltage, in the 5V case this is 3.33V, while the minimum considered for LS to be 1 is about 2.4V). HCT has TTL compatible input thresholds and will function properly when driven by TTL input signals.
That being said, HC(T) outputs swing to very near the power supply rails, so logical 0 is very close to 0V, and logical 1 very close to 5V. In the case of the schematic given, the 08 ans 27 chips only drive the FPU pins or the 30 chip pins, so they are very lightly loaded, and the voltage levels for 0 and 1 will be close to theoretical 0V and 5V. This means the 30 chip can be either HC or HCT as the input voltages for 0 and 1 will be properly recognized in either case.

Regarding speed (propagation delay and edge rates) be careful as specs can be misleading. HC(T) chips internally operate at very low powers and the internal logic is very fast, though speed dependent on the power supply voltage and temperature. Under normal conditions, the internal logic is MUCH faster than LS TTL. However, in order to interface with the external world that used to be regular, LS or even S TTL, where static currents are required, the output stages of output pins are quite a lot beefier but also more dependent on loading. Lightly loaded and cool HC(T) can be way faster that specs would suggest, and indeed much faster than equivalent LS with no load. Indeed, it's also reasonable to expect they will run cool since the static power drain of HC(T) is virtually zero, so unlike LS it does not heat itself even doing nothing.
The down side is that maximum power drain occurs when signals change, producing sharp current peaks in the power supply and ground. Although the average is far lower than LS, the peaks can be shorter so PCB line inductance will play a bigger role. Simply put: replacing lots of LS with HC(T) can result in problems with some marginal PCB layouts.

In the proposed schematic, LS (or ALS) should work fine, just expect more current draw from the power source. In either case (LS or HC(T)) be sure to do as good a job as you can with power decoupling and grounding - so my suggestion here would be to carefully reconsider the design you have made. Miniaturizing the PCB is only desirable goal, but it cannot replace good layout when the actual signals are concerned.


tcat
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Re: 74HCxx vs 74LSxx

Postby tcat » Tue Aug 13, 2019 12:32 pm

Hi Nasta,

Thank you for explaining, re `power decoupling and grounding', I tried to put a capacitor close to VCC of each chip. Power comes through P2 connector, which should connect to common +5V rail inside ST machine (have no idea yet where best to source, seeking advice), connector P1 should interface to CPU pins using ribbons.

Proper design with ground filled areas, so far beyond my capabilities, something I need to learn yet.

Tomas


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Re: 74HCxx vs 74LSxx

Postby tcat » Fri Aug 16, 2019 12:42 pm

Hi,

Just spotted the application note `AN947', pointed a few posts above, is missing appendices B,C. Anyone having the full document?

EDIT
The document I have is `AN947_REV0.PDF', I guess REV0 stands for revision 0.
It just happens to miss some pages at the end, containing appendices B,C.

It is Motorola's document giving info on MC68881 coprocessor connected as a peripheral chip.

EDIT
Just found A,B,C appendices in the form of source text.

Many thanks
Tom


tcat
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Re: 74HCxx vs 74LSxx

Postby tcat » Mon Sep 09, 2019 11:22 am

Hi,

No idea it will work in the end, but this is how it may fit inside my STFM machine. P1 should connect to CPU pins using ribbons, at least that is the idea so far, but there is RP7 red component getting in the way on one CPU side!!! Inevitably the ribbon will partly cover CPU from top, any precautions here, to allow CPU dicipate its heat properly?

Many thanks
Tom
Attachments
sfp004-mc68k-2.jpg
inside ST machine


stephen_usher
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Re: 74HCxx vs 74LSxx

Postby stephen_usher » Mon Sep 09, 2019 9:04 pm

Just be aware that different STF(M) revisions have the components in different locations.

This may be a useful resource: https://www.exxoshost.co.uk/forum/viewforum.php?f=41


Nasta
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Re: 74HCxx vs 74LSxx

Postby Nasta » Tue Sep 10, 2019 2:11 am

Shouldn't be a problem, the 68k CPU does not dissipate that much heat so hat being partially occluded by a ribbon cable would be a big problem.


tcat
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Re: 74HCxx vs 74LSxx

Postby tcat » Thu Sep 19, 2019 1:11 pm

Hi,

I have only a simple `pistol' soldering iron, and I am not very skilfull with it. This is what I have, ICs populated in the sockets, VCC/GND sourced around PSU connector.

GEM-BENCH reports some 1400% on FPU math test, while SYSINFO reports NO-COPROCESSOR fitted.

What does it actually mean?

Many thanks
Thomas
Attachments
sfp004-fitted2.JPG
DIY FPU populated and fitted inside ST


tcat
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Re: 74HCxx vs 74LSxx

Postby tcat » Fri Sep 20, 2019 10:58 am

Hi,

As my soldering is not very neat, I am no way sure I had it functional. I run this simple test that was coded by a German ATARI branch years ago.

sfp004-test-2.JPG
Running FPU math test

This may be an indication, it hopefully works?
Thomas



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