The Sinclair QL Forum

Derek_Stewart wrote:Hi,

As I mentioned earlier, I was redrawing the Minerva MkII PCB, from the original PCB I have, with a view to producing some more PCBs, do you think this is a good idea?

Silvester wrote: If you do build some beware of the green trimmer capacitors, I bought 50 from China and only half worked. The fault is the way the plastic case is crimped closed - the internal components are OK quality. There is a leaf spring contact at the base which is undermined during crimping, it can be restored by removing and retensioning. (I bought a DSO138 which had two trimmers, one of which didn't work because of same problem).

Silvester wrote:A useful mod to original MK2 might be to provide link to allow 48K or 64K EPROM.

Derek_Stewart wrote:Could a fixed capacitor not be used?

Derek_Stewart wrote:

Silvester wrote:A useful mod to original MK2 might be to provide link to allow 48K or 64K EPROM.

Maybe a good idea, but this would disable the Rom Port.

Silvester wrote:

Pr0f wrote:so looking at those stripped circuit boards - the chip under the ROM was a 13 Input NAND gage - so presumably used to do the finer address decoding for the SDA / SCL

Using a 7430 (8 input NAND) would have been enough, SGC allows direct access through to $BF80-BFFF. Here's something I wrote a few years back (for my own reference in case I forgot) if it's any help.

Code: Select all

Minerva MK2 hardware
~~~~~~~~~~~~~~~~~~~

                SDA __  __ SCL
                      ||
A4          $BFDC   1100
A5          $BFDD   1101
A2          $BFDE   1110
A3          $BFDF   1111

SCL is written by A0, SDA is written by A1
SDA is read into data bit 0 (whereas write is A1). Is SCL read on data bit 1 ?

SGC & GC provide access windows at 0000-0007 (false read for MHD) and 128 bytes
readable at BF80-BFFF (real read for I2C etc). Proven by logic probe on ROMOEH.

First use of RTC is in ss_ramt_asm to initialise and deal with D1 reboot value.

SGC/GC v2.49 copies OS 0000-BFFF to ram, this would upset I2C momentarily. When
Minerva reboots it would do another initialise of I2C.

Don't know other hardware that might use top 128 bytes of OS area.

JS rom BFE2-BFFF vectors and version string, this is referenced internally!

So I can only assume that any reads at $BF80-BFFF resort to slow read of OS
ROM (like ROMport $C000-FFFF), else JS ROM would fail to find vectors.

-----------------------------------------------------------
SGC uses timing loops CACHE_OFF:
                                  QL      GC      SGC cache_off
        moveq   #12,d0            8       4       3
wait    subq.l  #1,d0             12      8       3
        bne.s   wait              18/12   10/8    9/5     taken/not

target = 44cycles, 5.852uS  original Minerva

QL   32 + 30*(n-1) = 384c = 51uS        #1 = 32 + 12 (!) = 44 = 5.852
GC   20 + 18*(n-1) = 218c = 13.625uS    #5 = 20 + 18*4 = 94c = 5.75uS
SGC  11 + 12*(n-1) = 143c = 5.96uS

! 12 is assumed from following instruction

------------------------------------------------------------

Special byte: 1 1 G V D C 1 Q
                  | | | | | |___ quit
                  | | | | |
                  | | | | |_____ must be 1 else err_bp
                  | | | |
                  | | | |_______ SCL
                  | | |
                  | | |_________ SDA
                  | |
                  | |___________ 0 kill bus to free state SCL=1, SDA=1
                  |              1 assume bus valid
                  |
                  |_____________ 0 device group is parameter value
                                 1 device group is in register

V=0 D=0 C=0 is invalid

Finish command buffer with special byte $FF, or where bus is not being
released between calls $F3 keeping SCL and SDA low.

    I/O byte: 1 0 S R B P A 0
                  | | | | | |___ must be 0 else err_bp
                  | | | | |
                  | | | | |_____ send ACK if R=1 on last read
                  | | | |
                  | | | |_______ send STOP
                  | | |
                  | | |_________ 0 R=0 destination is register
                  | |            0 R=1 source is control
                  | |            1 source/destination is data buffer
                  | |
                  | |___________ 0 write
                  |              1 read
                  |
                  |_____________ send START


R=0 A=1      is invalid
R=1 P=1 A=1  is invalid

NB. There appears to be a bug in GC & SGC speed patch versions. If you give
10x11010 ie. read into data buffer with no-STOP sent and do ACK on last byte.
Then it will send STOP because B is misinterpreted.

Also Phil Borman's copy for SGC SMSQ does same.

Derek_Stewart wrote:Hi,

I have Minerva MkII that I was repairing broken pins on the Rom Socket.

But I decided to remove the complete Rom Socket and see if I could reverse engineer the PCB. As Tony Firshman sent all his Minerva Stuff into the Texas Black Hole...

Here are photos of the Minerva MkII PCB minus the ROM Socket.

MinervaMKII-1.jpg

MinervaMKII-3.jpg

Pr0f wrote:Some good notes there - SCL is never read - as this is the I2C clock - and as the Minerva implements it as a single Master role - the QL always drives the clock - the SDA signal on the other hand needs to be read and written.

QViewStu wrote:Not sure if that board was tested working but the GAL is the wrong way round unless my eyes deceive me…

Silvester wrote:

Pr0f wrote:Some good notes there - SCL is never read - as this is the I2C clock - and as the Minerva implements it as a single Master role - the QL always drives the clock - the SDA signal on the other hand needs to be read and written.

Never having had Mk2 Minerva hardware I wasn't sure whether SCL read had been implemented in GAL (ROM routines act only as master). It was trivial to add though.

Silvester wrote:

QViewStu wrote:Not sure if that board was tested working but the GAL is the wrong way round unless my eyes deceive me…