ULA ZX8301 - TV Picture Capabilities

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Martin_Head
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Re: ULA ZX8301 - TV Picture Capabilities

Postby Martin_Head » Wed Sep 13, 2017 11:04 am

When you said
tcat wrote:My TV is quite a modern Thomson make, it gives excellent picture with ZX Speccy and ATARI ST, all in TV mode, no flair in white.
QL Picture over RGB-SCART cable is also perfect.
was that cable RGB only, or was that using composite video? If the picture using composite video is OK. Then it looks like the MC1377 is working Ok. And I would just replace the UHF modulator before worrying about anything else.


Nasta
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Re: ULA ZX8301 - TV Picture Capabilities

Postby Nasta » Wed Sep 13, 2017 11:22 am

tcat wrote:Hi Nasta,
Thank you, I was hoping for and awaiting your comment, too :-)
Now again studying `QL Service Manual' and Issue#6 diagram. It says composite PAL signal is output/divided to UHF Modulator, capturing in the picture, when you say lowering amplitude, you mean changing values of the resistors R85/R86, how?
PAL-UHF-feed.png
Could it also be some of the modulators' transistors being degraded, worth replacing?
Many thanks so far.
Tomas


I suppose there could be a problem with the transistors but I would not say it is highly probable.
Regarding the resistors, perhaps increasing R85 from 100 ohms to 120 or 150.
The general problem with QL screen output is that it is internally routed from the 8301 which is all the way on the left-hand side, to nearly all the way on the right-hand side, through long lines that are handled as if they were digital, but in the end get to be interpreted as analog. This means that both when they are low and high, the signal has a whole lot of hash superimposed on it. So a lot of stuff can interfere.


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Re: ULA ZX8301 - TV Picture Capabilities

Postby tcat » Wed Sep 13, 2017 5:19 pm

Hi Martin,

ZX/ATARI over UHF modulated TV cable, picture is of good quality, this may exclude TV from fault finding, I should think.
I did not try QL composite output, that would require feeding the signal to a yellow input socket on my TV, also bypassing modulator is needed for that, to get composite signal, I guess. Tried only RGB over SCART that is good, though.

Hi Nasta,

I will toy with R85 value as suggested, perhaps I may bridge it in parallel with the same value, that's an easy test for me. White flair appears as if of some kind of digital pattern. I cannot therefore help thinking about PENCL signal, could it be the cause of picking noise in modulated video?

Many thanks all so far.
Tomas
Last edited by tcat on Thu Sep 14, 2017 8:19 am, edited 1 time in total.


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Re: ULA ZX8301 - TV Picture Capabilities

Postby Nasta » Wed Sep 13, 2017 7:38 pm

Putting a resistor in parallel with any other resistor results in a resistance value which is ALWAYS LESS than either of the two in parallel. So in this case you might try it with R86.


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Re: ULA ZX8301 - TV Picture Capabilities

Postby Martin_Head » Thu Sep 14, 2017 10:48 am

tcat wrote:Hi Martin,

ZX/ATARI over UHF modulated TV cable, picture is of good quality, this may exclude TV from fault finding, I should think.
I did not try QL composite output, that would require feeding the signal to a yellow input socket on my TV, also bypassing modulator is needed for that, to get composite signal, I guess. Tried only RGB over SCART that is good, though.

The SCART socket on the TV should have a video in pin 20, use pin 18 as ground. The composite signal is available on the RGB socket on the QL (pin 1, and pin 2 for ground http://www.dilwyn.me.uk/docs/hardware/monitor%20connections.jpg) You should just need a piece of screened cable between the two. There is no need to bypass the modulator, or even open the QL.


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Re: ULA ZX8301 - TV Picture Capabilities

Postby Nasta » Tue Nov 28, 2017 9:17 am

Details of ZX8301 operation coming soon :)


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Re: ULA ZX8301 - TV Picture Capabilities

Postby Dave » Tue Nov 28, 2017 6:47 pm

I've had a sneak preview... It's a Sinclair doozy!

You're gonna love it so hard you're gonna cry.


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Re: ULA ZX8301 - TV Picture Capabilities

Postby Nasta » Wed Nov 29, 2017 1:49 pm

Preliminaries:

How was it done?
The following information has been gleaned from measurement rather than reverse-engineering the posted micro-photo of the 8301 chip, lest someone thought I'm some kind of reverse-engineering genius :)
The 8301 does not do complicated things, as can be seen from the actual capability and existing documentation, so it was easier to connect a logic analyzer to a QL motherboard and see WHAT it actually does in certain circumstances and infer the important parts of how it does it from that, rather than from the actual logic (which would be far more complicated).

What 8301 and motherboard version was used?
The 8301 in question is the ceramic CLA version, and the motherboard is an issue 5. I am pretty certain there is not much difference between the 8301 versions although I intend to check this out when I get some time. That being said, there IS a difference in how the 8301 is connected on issue 5 boards, versus all the newer ones - the latter being recognizable by the inclusion of the HAL chip (which is basically a hard-coded PAL). There will be a fair amount of discussion on this.
No expansions were addeed, this is a bare motherboard (literally) with a Minerva ROM on it.

What was measured?
The logic analyzer I have at my disposal has a maximum of 16 digital and 2 analog inputs (it is an older HP mixed signal digital scope). To get the most information out of a single measuring setup, the following lines were monitored:
On the expansion connector:
From the CPU: A6, A15, A16, A17, DSL, RDWL
From the 8301: CLKCPU, DTACKL, ROMOEH, CSYNCH
On 8301 pins (as these signals do not appear on any connector): RASL, CAS0L, WEL, ROWL, VDA, TXOEL
This makes a total of 16 digital signals. For one measurement one analog input was used to trigger measurement, with VSINCH as the input.

How was the operation reconstructed from measurements?
The HP scope can sample it's digital and analog inputs at up to 200MHz rate with the configuration used and has a 2 meg sample capacity per measurement. It can be configured to start, center or end sampling using definable conditions, so the conditions were varied as the functions became more and more clear, to get more detailed information.
For instance, since we know the 8301 does decoding, DRAM control and video screen refresh (tightly coupled with DRAM control), and the functions of some signals are known from the connections in the schematic, the first measurement was triggered by CSYNCH. The storage capacity of the scope is enough to capture all signals within a single display line, with enough time resolution to get an idea what happens when. Then, additional trigger conditions were set up to investigate in detail. For csynch we know it's a negative going pulse (but changes to positive when VSYNCH is active, which is only a fraction of the total time), and it occurs every 64us or very close, since that is defined in the TV standard the QL screen generation is compatible with. If we divide that with 2M 'records' we get about 30ns, the closest setting on the scope being 50ns. Given that the clock period at 7.5MHz is 133.333ns, it's not going to be the most precise picture but a good start.


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Re: ULA ZX8301 - TV Picture Capabilities

Postby Nasta » Wed Nov 29, 2017 2:40 pm

Results - the short version:

The unexpected:
It is quite possible that the 8301 and 8302 designs started life as a single large design, to be put into a larger chip. In particular the way the 8301 and 8301 are connected together on issue 5 boards and the way 8301 does decoding for 8302 and it's own internal registers, points to this - as well as some history. At the time the QL was developed, Sinclair's arch-nemesis Acorn had just put out the Electron, which was an attempt to cut down something similar to a BBC micro to Spectrum prices, using a high integration custom chip. Acorn however had big problems with that, which is why Sinclair might have defaulted to Ferranti et al, being well experienced in the technology, but had to split the design into two chips. More discussion on this will follow, as issue 6 and later boards do not follow this connection convention, which, if it had not been followed from the start, would have resulted in opportunity to put some much needed added functionality into both the 8301 and 8302.

The simple:
8301 is the main system decoder, and it has to decode and map the following devices into (part of) the 68008 address space:
1) ROM (64k)
2) IO (64k - of which actually 16k is used, this includes the internal control register of the 8301, and the 8302)
3) RAM (128k, in two banks of 64k)
Total 256k space used on-board.
ROM is explicitly decoded using the ROMEH pin on the 8301 which goes to the J1 connector and both ROM sockets. A small reminder here - both ROM sockets are connected dead parallel. The chip select polarity options in the ROM chips themselves are used to decode the 32k and the 16k ROM in their proper place. The trick is that socket pin A15 is n active low chip select pin on the 32k ROM, and active high chip select pin on the 16k ROM. Additionally, socket pin A14 is a regular address line (A14) on the 32k ROM, and an active low chip select on the 16k ROM. Both ROMs also have an active high chip select on the socket pin ROMOEH.
The 8301 has only two address pins, those being A17 and A16. This, however is enough to decode the total 256k of stuff used on the motherboard, as A17 and A16 decode 4x 64k blocks - one for the ROM, one for the IO, and one for each of the two RAM banks of 64k.
Along with DSMCL (which is actually equal to DS when no expansion is present) and RDWL (also a pin on the 8301), this is enough to decode ROM read - simply, when A17 = A16 = DSMCL = 0 and RDWL = 1, ROMOEH=1. That's all there is to it.

The complex:
Since the 8301 is tasked with showing RAM data as a picture on the screen, and that process is a synchronous one, which has to be maintained with exact timing all the time, a good assumption to make is that transferring RAM data to the screen has priority over everything else, or, in this case, any CPU access to the RAM.
The peculiarity here is, that the 8302 data bus is, on issue 5 boards, connected to the 8301 data bus, together with the RAM data bus - and this is NOT directly connected to the CPU bus, but rather through a data bus transceiver (72LS245) and address bus multiplexers (2x 74LS257).
These chips disconnect the CPU when the 8301 needs to access RAM in order to read screen data. Because the 8302 is connected to the RAM side rather than the CPU side, on issue 5 boards, the 8301 is accessed with the same restrictions as the RAM is.
The basic mechanism of operation is as follows:
The 8301 uses the signal VDA (Video Data Access, presumably) to periodically disconnect the CPU from the RAM, by switching off the address multiplexers that multiplex the CPU address lines into a multiplexed version suitable for dynamic RAM as used in the QL, and superimposes it's own signals onto these lines.
If the CPU is not accessing RAM or IO, TXOEL is also high, disconnecting the RAM (AND 8302 on issue 5 boards!) from the CPU bus, which would be normal for a device that is not addressed.
Nothing special happens further if the CPU is accessing ROM - as it's not RAM or IO, ROM access is performed at full speed and the CPU is none the wiser.
However, MUCH more interesting things happen if the CPU has to access RAM or IO.
RAM access has to be done with strictly defined timing, which is implemented as a state machine in the 8301 DRAM controller logic. If the CPU sets DSL low, and either A17 is high (which means it want's to access RAM) or A17 is low but A16 is high (which means it wants to access the IO area), if there is not enough time to perform a RAM access before the 8301 has to start reading screen data, it will ignore the CPU request until the screen data is read, at which point the CPU is given access (VDA goes low) and the appropriate RAM control signal sequence (RASL, CASL, WEL, ROWL) is executed, amidst which TXOEL is also set low to connect the RAM bus to the CPU, so that data can be transferred. The CPU is kept waiting by the 8301 not setting the DTACKL signal low until the proper moment inside the RAM signal sequence, preventing the CPU from assuming the data is present before it actually read, or ending the access and removing the data before it is actually written.
If the 8302 is accessed, a 'fake' RAM signal sequence will be performed, but neither of the CASL lines will be set low, so that the RAM will just be refreshed and keep it's data lines inactive, while the PCENL line will be pulled low and the 8302 will be active instead, either reading or writing data as needed.
When A17 is high, A16 is used to determine which one of the CASL lines is to be activated, as each controls one 64k RAM bank. All the other RAM control signals are common. As mentioned before, when A17 is low and A16 high (meaning IO access, which is either the 8302 or the internal MC control register in the 8301), neither CASL is generated, but rather PCENL is generated IF A6=0. When A6 is 1, the MC register in the 8301 is written.
At this point one might ask where does the 8301 get the address line A6 from, since there is no pin named A6 - more on that follows.



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