OPD: Computer One floppy interface recreation.

[stephen_usher]

The field notes document seems to be a manual for a "high speed serial" interface card. The other two documents are a service FAQ and a system overview for BT field service engineers.

[stephen_usher]

So as to do a bit more of a test of the ROM socket I desoldered the ROM in the VT-Link cartridge.

The pins had been cropped really short so they wouldn't connect into the EPROM programmer ZIF socket. Thankfully I had a dual-wipe socket handy so pushed the EPROM into that and then it read fine.

With a W27512 programmed with the data and in the floppy board the machine now crashes when looking for the option ROMs, which isn't unexpected given that the normal ROM size is 32K but there's only a 16K memory window for the floppy system ROM.

Anyway, it does mean that I can post the VT-Link ROM image. (attached)

[Pr0f]

Did you get the ROM image for this recreation Stephen?

[stephen_usher]

Not yet. Someone is going to send the ROM to RWAP who's going to image it and then send me the image.

[Pr0f]

So I was looking at the circuit with a view to simplifying it.

I am uncertain as to the purpose of the 74LS74 flip flops in the circuit - in the ROM modules, pin 27 is just simply grounded to indicate the presence of a device in the ROM slot - surely that could also be used here - saving a whole chip and one gate.

Another 3 gates could be saved by using a crystal oscillator module, and the various drivers used for interfacing to the floppy drive could be reduced to a single 20 pin 74LS240 chip - used in a lot of the QL disk interfaces.

The ROM chip has to stay, the LS245 interface for the data bus - probably a good idea to keep that. The Floppy disk controller too.

So that leaves the other select logic and address decoding and the 4 latches (74LS175). This could probably all be tied into a GAL 16V8 in registered mode, and one mosfet to invert (open drain) the interrupt from the FDC chip.

I have not tested this - or tried compiling it yet - but the following logic:

175_clk 1 20 VCC
/DSL 2 19 /175_CE
/CE 3 18 /ROMOE
A14 4 17 /FDC_CS
A13 5 16 SEL0
D0 6 15 SEL1
D1 7 14 SIDE
D2 8 13 /FDC_Reset
D3 9 12 R/W (in)
Ov 10 11 Ov (/OE)

/ROMOE = /DSL * /CE * R/W * /A14
/FDC_CS = /DSL * /CE * A14 * A13
/175_CE = /DSL * /CE * /R/W * A14 * /A13
(175_clk tied to /175_CE externally)

SEL0 := D0
SEL1 := D1
SIDE := D2
/FDC_Reset := D3

would seem to address what's needed - /DSL is called /OE on the C1 interface diagram. D0-D3 would be ID0-ID3 on the interface (buffered by 74LS245)

[stephen_usher]

The 74LS74 is really not needed. Normal ROMs probably only pull the line low when /CE and /OE are send from the host interface. What the circuit in the interface is doing is effectively pulsing the line high every clock cycle for a few nanoseconds, which makes zero sense.

[Pr0f]

I pulled the lid off a ROM module, and pin 27 is just tied to ground. The resistor - value 2.7K goes from +5v to pin 1 of the Eprom, and the capacitor is tied between 0v and +5v. I think the same tying to ground would work perfectly well for the disk interface. I think the ICL OPD only decodes the /CE for the module if that pins is grounded, indicating a ROM is present.