Q40 - RAM mapping

[Nix]

Can anyone clarify the Q40 RAM mapping?

From what I gather RAM is mapped from 0x00000000 to 0x01FFFFFF when fully populated with 32MB
The question arises when 4MB SIMMs are involved. In the case of 4MB or 20MB installed, the manual says that:

If 4 MB (20 MB) DRAM are installed, accesses beyond $003F FFFF ($013F FFFF) are mirrored to (upper) 4 MB.

My question is: Where exactly is the RAM mirrored?

I don't have a 4MB SIMM, so I can't test it out, and although this is a purely experimental development, it would be nice to be complete, so that, should anyone else what to play with it, it will work, regardless of RAM configuration.

Nick

[Derek_Stewart]

Hi Nick,

The Q40/60 can access 32Mb ram of continuous memory.

The SMSQ/E operating system can use up to 64Mb ram.

To access the 128Mb ram, there requires a hardware modification to the circuit board.

But with this modification, there is no change to to the SMSQ/E memory access. However, under Linux, 128Mb is available.

[Nix]

Hi Nick,

The Q40/60 can access 32Mb ram of continuous memory.

The SMSQ/E operating system can use up to 64Mb ram.

To access the 128Mb ram, there requires a hardware modification to the circuit board.

But with this modification, there is no change to to the SMSQ/E memory access. However, under Linux, 128Mb is available.

I'm not sure you read my question properly.

Nick

[Peter]

My question is: Where exactly is the RAM mirrored?

This info has never been needed yet. For me 1997 is too long ago to answer it without significant effort.
It is sufficient to do a memory presence check in 4MB steps.

[Nix]

My question is: Where exactly is the RAM mirrored?

This info has never been needed yet. For me 1997 is too long ago to answer it without significant effort.
It is sufficient to do a memory presence check in 4MB steps.

Great! Thanks Peter, that's all I needed to know. If it were mirrored immediately after, then it would have been a problem.

Nick

[ansar]

Dear nix,

In case that actual memory addresses are needed for a good reason then:

If you have:
- 1 simm of 4Mb then ram addresses are:
0FFFFF, 1FFFFF, 2FFFFF and 3FFFFF
for each Mb
- 2 simm of 4Mb then ram addressses of
1st simm as above and the 2nd simm:
3CFFFFF, 3DFFFFF, 3EFFFFF and 3FFFFFF
- 3 simms of 4Mb then ram addresses of
the 1st and 3rd simm will be as abov
and the second simm will be:
38FFFFF, 39FFFFF, 3AFFFFF and 3BFFFFF
- 4 to 7 simm in a similar way
- 8 simms of 4Mb as 1 of 32Mb
- 1 simm of 20Mb then ram addresses are:
0FFFFF to 13FFFFF
- 1 simm of 20Mb and 1 simm of 4Mb then
addresses of 20Mb as above and
addresses of 4Mb simm will be:
3CFFFFF, 3DFFFFF, 3EFFFFF and 3FFFFFF
- 1 simm of 20Mb and 2 simm of 4 Mb then
1 simm of 20Mb and 2nd simm of 4Mb as
above and the 1st simm of 4Mb willbe:
38FFFFF, 39FFFFF, 3AFFFFF and 3BFFFFF
- 1 simm of 20Mb and 3 simm of 4Mb as
one sim of 32Mb

Regards,
ansar

[Peter]

My question is: Where exactly is the RAM mirrored?

This info has never been needed yet. For me 1997 is too long ago to answer it without significant effort.
It is sufficient to do a memory presence check in 4MB steps.

Great! Thanks Peter, that's all I needed to know. If it were mirrored immediately after, then it would have been a problem.

Typically you would write some non-mistakable values in 4MB steps (e.g. address as longword data) top down (of course making sure not to hurt your own data/code) and then check bottom up, up to which region they are correct.

[Peter]

- 4 to 7 simm in a similar way [...]

We are not talking a PC but a 68040 mainboard with just two SIMM sockets.