An internal upgrade occupying the vacant ROM socket after moving both ROMs into one (and including the TKII). The ram chip is an 512k x 8 low power SRAM and the glue logic is done with a GAL 20V8
The GAL chip is mounted on a piece of Veroboard which is soldered to the 4 extra pins of the SRAM which then is put into the ROM socket with its remaining 28 pins to keep the low profile.
Good news: it works.. well almost perfect. The signal generated for the DSMCL line is very 'touchy'. You can not connect the oscilloscope's probe to it without the QL crashing. I used the /DS line as strobe for the various output signals but mayby /AS is better as it is more constant/longer. /DTACK is also generated from /DS combined with some address logic. No need for delays here as the SRAM is 55ns
The GAL also generates the inverted
select signal for the EPROM which is OK now.The pictures show the initial trials, I will try to find some of the signals closer to the GAL chip so the long cables can be shortened.
- 512k SRAM with accompanying GAL chip
- Using FREE_MEM to show amount of free RAM
Both /DTACK and DSMCL are programmed to be Tri-State (floating) when not active. Created one pin to reflect the validity of the memory range and used that to enable the output of /DTACK and DSMCL signals from the GAL
