Q68 I2C Driver

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Derek_Stewart
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Re: Q68 I2C Driver

Post by Derek_Stewart »

Hi Martin,

Thank you for the update,I must say the assembler source code looks good, I like the way you have used the Minerva I2C code.

Does the Auto Configuration use the Q68 Fast Memory if available?


Regards,

Derek
Martin_Head
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Re: Q68 I2C Driver

Post by Martin_Head »

Derek_Stewart wrote:Hi Martin,

Thank you for the update,I must say the assembler source code looks good, I like the way you have used the Minerva I2C code.

Does the Auto Configuration use the Q68 Fast Memory if available?
What it does, Is that it just looks to see where in memory the driver has been loaded. Then adjusts the delays required in the transmissions to keep about the same bitrate in both the normal and the fast memory. (Where the driver runs quicker in fast memory)

It's down to you where in memory the driver is loaded. The test it does is a bit quick and dirty. If the start address of the driver is in not in the fast memory area, then it assumes it's in the normal memory area.


Martin_Head
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Re: Q68 I2C Driver

Post by Martin_Head »

I noticed that the backup clock on my Q68 started playing up. The backup clock would stop when the Q68 was switched off.

So if I turned if off at 2PM, then switched it on the next day. DATE$ wound say that it was 2PM yesterday.

I don't know exactly when this happened, But I expect it was when I was playing around doing the I2C driver.

If anyone else has problems with the Q68's backup clock this program will read and reset the RTC chip

Code: Select all

600 REMark Read Q68 RTC chip
610 x$=CHR$(164)&CHR$(0) : REMark Address device
620 x$=x$&CHR$(10)&CHR$(188) : REMark Read 10 bytes
630 x$=x$&CHR$(255) : REMark Terminate cmd
640 t$=I2C_IO(x$,10,104,1)
650 FOR n=0 TO 9
660   PRINT n,BIN$(CODE(t$(n+1)),8)
670 END FOR n
680 STOP
690 :
700 REMark Reset the Q68 RTC chip
710 REMark Clear all registers
720 x$=CHR$(164)&CHR$(0)
730 FOR n=1 TO 10
740  x$=x$&CHR$(0)
750 END FOR n
760 x$=x$&CHR$(255)
770 t$=I2C_IO(x$,0,104,11)
780 STOP
790 :
In my case I think the source of the problem was that bit 7 of register 7 was set.

After resetting, Register 9 gets set to 10101001 after a system restart. I assume this is done during power up to set up the charging of the backup cap.


Derek_Stewart
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Re: Q68 I2C Driver

Post by Derek_Stewart »

HI Martin,

The Q68 Clock setting is preserved by using a Super Capacitor that stores enough charge to backup the Clock settings.

If the Q68 is left unpowered for a long length of time, the Super-Cap maybe of become discharged, so the clock setting is 0 or the default for SMSQ/E. I never really had that problem, as he Q68 is not powered down.

I suppose a possible change would be to fit a Backup battery in place or in parallel with the Super-Cap.


Regards,

Derek
Martin_Head
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Re: Q68 I2C Driver

Post by Martin_Head »

Derek_Stewart wrote:HI Martin,

The Q68 Clock setting is preserved by using a Super Capacitor that stores enough charge to backup the Clock settings.
That was my problem. Some of the IC's registers had got corrupted, and the Super Capacitor was retaining the bad registers. I would have had to either remove the super capacitor, or discharged it to reset the registers.

I suppose the Q68SETRTC executable could be rewritten to clear the registers that got corrupted.
I suppose a possible change would be to fit a Backup battery in place or in parallel with the Super-Cap.
That would be a question for Peter. But I think you would also have to change something in the systems boot up code, that writes to the RTC chip to set the trickle charge for the battery, or disable it entirely if a non rechargeable battery is used.


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Peter
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Re: Q68 I2C Driver

Post by Peter »

Martin_Head wrote:But I think you would also have to change something in the systems boot up code, that writes to the RTC chip to set the trickle charge for the battery, or disable it entirely if a non rechargeable battery is used.
Indeed one can not simply add a battery without changing the bootloader code as the RTC would try to charge it.
If longer data retention is desired, a higher capacity SuperCap can be used instead of (or parallel to) the existing one.


Martin_Head
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Re: Q68 I2C Driver

Post by Martin_Head »

This program sets the backup clock to the current time. The same as the Q68SETRTC executable. Unlike the executable, It also resets the Watchdog/Alarm Counter, and the Control and Status registers. And sets the Trickle Charger to the Q68's power up setting.

Code: Select all

800 REMark Enhanced Q68SETRTC
810 REMark Set backup clock to current time
820 x$=CHR$(164)&CHR$(0)
830 a=PEEK_L($18000)
840 a$=HEX$(a,32)
850 x$=x$&CHR$(HEX(a$(7 TO 8)))
860 x$=x$&CHR$(HEX(a$(5 TO 6)))
870 x$=x$&CHR$(HEX(a$(3 TO 4)))
880 x$=x$&CHR$(HEX(a$(1 TO 2)))
890 FOR n=1 TO 5
900  x$=x$&CHR$(0)
910 END FOR n
920 x$=x$&CHR$(%10101001)
930 x$=x$&CHR$(255)
940 t$=I2C_IO(x$,0,104,11)
I know it gets a bit convoluted around line 840. But PEEK($18000) don't work, it just returns zero. PEEK_W and PEEK_L are OK. Also PEEK$ returns zeros.
I tried PEEKing $18000 in Qemulator under QDOS, and that worked OK. So I don't know if its a SMSQ/E or a Q68 thing.


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Pr0f
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Re: Q68 I2C Driver

Post by Pr0f »

Does the Q68 have a free running seconds counter at address 18000?


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Peter
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Re: Q68 I2C Driver

Post by Peter »

Pr0f wrote:Does the Q68 have a free running seconds counter at address 18000?
Yes, a 32 Bit counter. Only longword access is allowed.
There is a latching mechnism which prevents number roll-over between the two 16-bit accesses on the bus.
The bootloader initializes the counter from the value provided by the buffered RTC.


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Pr0f
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Re: Q68 I2C Driver

Post by Pr0f »

Peter wrote:
Pr0f wrote:Does the Q68 have a free running seconds counter at address 18000?
Yes, a 32 Bit counter. Only longword access is allowed.
There is a latching mechnism which prevents number roll-over between the two 16-bit accesses on the bus.
The bootloader initializes the counter from the value provided by the buffered RTC.
Thank you for clarifying that Peter.


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