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Re: How to reliably detect USER or SUPERVISOR mode across CPUs

Posted: Sat Apr 27, 2019 2:29 pm
by tofro
Nasta wrote:
Dave wrote:How might detecting this tie in with detecting and enabling caches on the 68000, 68020, 68030 and 68060?


Enabling cache on a 68000 is REALLY hard.


Detecting it is even harder ;)

In earnest: You don't detect cache on a 68k CPU (some cache modes make it impossible to be "seen" by the CPU itself) - you rather detect the CPU and then "know" the cache type and mode.

That is done by exploiting subtle (or not so subtle) differences between CPUs. The brute-force method is to try instructions or addressing modes that were only available on later CPUs and see if they trap out (you must be catching the exception though, which is a bit complicated). If your CPU does allow non-word-aligned word access, it must be >= 68020, there are also some small differences with post-increment and pre-decrement (move (sp),-(sp)) modes that can be used to detect the CPU you're working with.

Tobias

Re: How to reliably detect USER or SUPERVISOR mode across CPUs

Posted: Sat Apr 27, 2019 5:08 pm
by Dave
Well, then it fails on detecting the cache :P

Re: How to reliably detect USER or SUPERVISOR mode across CPUs

Posted: Sat Apr 27, 2019 10:09 pm
by Peter
A good example for detecting and initializing various CPU types is found in QDOS Classic, attached.
It creates a set of flag:

bit 0 - at least 68010
bit 1 - at least 68020
bit 2 - at least 68030
bit 3 - at least 68040
bit 4 - at least 68881 (possibly 68882)
bit 5 - 68882 present (or emulation)
bit 6 - 68040 or 68060 on-chip FPU enabled
bit 7 - at least 68060