Dave wrote:I am currently favoring the idea of smaller, pre-decoded expansion slots with a 16- or 32K addressable area, plus an SPI interface. If the slots are empty, then RAM can be enabled in the empty space.
Whichever route is taken, the objective needs to be clear.
What is the intended use of any expansion connector?
Given that the QL scene is small, what is the likely-hood of any actual new spec. expansion cards being produced?
If it is to include compatibility with the existing QL expansion connector, what existing cards are going to be supported (someone somewhere will want something to work, computer history is littered with this kind of thing). Maybe include a separate QL expansion connector just for existing expansion cards?
For new peripherals, if drivers can be developed maybe only USB should be supported for new peripherals devices? Not that I am particularly in favour of USB on retro machines, but it is the route mainstream computers are going...
Of course, some of the answers will depend on exactly what features a new processor / motherboard will have. And in common with computers through history, predicting the future and getting it right is not easy
Mark
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QL, Falcon, Atari 520STFM, Atari 1040STE, more PC's than I care to count and an assortment of 8 bit micros (Sinclair and Acorn)(nearly forgot the Psion's)
I think it's fair to say that it is very unlikely that any mainstream expansion would need to be plugged in. The only expansions that would provide utility not already on the motherboard would be QEPIII Eprom Programmer, and ED floppy interfaces. However, a couple of the new features would make people a lot less inclined to use those two anyway.
The impractical side of me would like to see one old-school J1 on the left edge of the board, then three or four decoded expansion slots back left, where the PCIe slots would go on an ATX motherboard. All of the traditional connectors would be in the position where connectors usually go on an ATX board, and it would be supplied with a laser-cut gasket. This would then also be able to fit inside a QL case with everything from the right edge being clear for other use.
Nasta included a pre-decoded area on the Aurora, and nobody ever used it. I don't know how many Aurora were sold, but that's a problem in my mind. I don't know if it was undocumented (my Aurora came with nothing - no manuals, cables, anything)... I do know that Aurora is the one card I have never seen come up for sale.
The expansion proposal - whatever it may be, should make it easier and cheaper to design expansions - not the reverse. I think I have a strong BBC micro ethos that people should be able to casually build things, plug them in and have them be accessible.
I am secretly wishing for a GPIO expansion so I can control christmas tree lights next year! First World problems! I suspect the first real expansion card will just be an ED floppy adaptor.
1024MAK wrote:For new peripherals, if drivers can be developed maybe only USB should be supported for new peripherals devices?
I'd estimate the likelyhood that USB drivers will ever be written for the QL below 1%.
USB would almost certainly mean another little computer running the USB drivers, and connecting to the QL by a non-USB interface.
Second that.
Apart from very simple USB devices like mouse, serial or keyboard, the driver development for USB is a nightmare. Even (apparently) simple devices such as thumbdrives require a bloat of code to get them working.
The simplistic interrupt architecture of the QL doesn't help either. USB would most probably not work with the shared interrupt approach of QDOS.
(1) QL compatible peripheral boards must leave these pins open.
(2) Optional wide bus mode strobe. A CPU board that does not support this should have a pull-up here
(3) Not normally used in QL systems, but should be generated for full QL compatibility. Has dual function for CPU boards that support wide bus mode.
(4) May be tied to ground if the peripheral board is driving the bus (i.e. peripheral on-board CPU) or the CPU board does not support bus requests to it's on-board CPU. This is tied to ground on any board that connects to the QL J1 connector and wishes to disable it's on-board CPU.
(5) If a CPU board does not generate or support all of these extra address lines, it should put a meaningful and constant logic level on these lines. Actual levels depend on what the CPU board wants to achieve. Since the spec is based on a 16 meg address space (extended from the original 1 meg), the original ROM and low memory should still reside at the lowest addresses of the memory map, and the IO extension area at the highest addresses of the memory map. So if the CPU does not generate all of the above lines, the lines it does not generate should all be copies of the highest address line it does generate.
(6) Provided for QL compatibility, but should only be generated internally on the CPU board and not be used by peripheral boards.
(7) Should be phased out, provided for QL compatibility. Contains pull-down and will prevent any 8-bit hardware on the CPU board from being selected if pulled high, which can be done on an address by address basis. Implementing this whould be considered optional.
(1) This signal goes low to indicate a wide bus cycle.
(2) Reserved, normally low for 32-bit wide access.
(3) Left open in the GF spec as it was technically an expansion and can be used with a QL motherboard.
(1) This signal goes low to indicate a wide bus cycle.
(2) Don't care for 16-bit wide access.
(3) Left open in the GF spec as it was technically an expansion and can be used with a QL motherboard.
The expansion connector, in original and expanded forms, contains a lot of options for drawing power.
In the QL2 spec, the machine will have a total of 6A @ 12v DC supplied by an external well-regulated PSU. 2A is reserved for the motherboard.
VIN (9v nominal) is available on a31,a32,b32. As a rule, all three pins should be connected by any expansion. On QL2 this will probably be 12v nominal - still a subject of discussion. If this happens, we would make available at low cost a pin compatible switch mode PSU which can replace a 7805, operate at >95% efficiency, and handle <45V DC input. It won't even get warm.
+12V is available on a30. In QL2, this can supply up to a total of 2A to all expansions, combined.
-12V is available on a31. On the QL, this was limited to a few mA.
+5V will be available on b28 on QL2. This will supply 2A well regulated DC total to all expansions. It is intended for small, simple expansion cards that wish to remain lightweight. It's ideal for prototyping.
The use of voltage regulators like 7805s is gently discouraged. These are not efficient and create a large amount of heat. In combination, a largely expanded system could strain a 6A 12V supply. We are happy to supply a 7805 replacement PCB, or a schematic so you can incorporate an appropriately sized buck regulator system into your design.
There are a few errors in the above spec which I actually wrote but since then I had gone through the GF, Qubide and Aurora docs I still have. Some stuff in there is different and I was reminded why the particular decisions to make it so were made.
There are several pin definitions that should be changed or amended in the 8-bit mode spec:
Pin B5, Old ASL, New ASL (with extra note)
This signal should not be used on a QL however there are peripherals that do. The support for this signal should be considered optional, although it is possible for the motherboard to provide a signal that is highly compatible with the original function (for example, by duplicating the DSL signal from pin B6). Note however that this pin has an extra function when wide bus mode is supported.
Pin B6, Old DSL, New /NTRQ (currently marked /DS)
This pin provides the same functionality as the original DSL signal on the QL and should be near 100% compatible. It may be re-labelled as /NTRQ, for Narrow Transfer ReQuest.
Pin B9, Old BGL, New /WTRQ, currently marked /BG and should be re-labelled to /WTRQ
This pin was an output, when low it indicates that the QL motherboard CPU has been disabled. The new spec does not provide a means for the motherboard CPU to be disabled from the expansion bus, so the pin function has been redefined as the Wide Transfer ReQuest, if wide bus mode is supported. If not, the pin should be tied to +5V on the motherboard, and not used on peripherals.
Pin B10, Old BRL, New GND:
This is connected to GND on the motherboard side (male J1), and redefined as ground to provide an extra point to connect a ground plane for better signal intgegrity. If a peripheral is designed that should also run on the QL, this pin should be left open. However, if it is designed to run in an original QL or Aurora system that uses a GC or SGC _only_ it can be left connected to ground, as both GC and SGC (And Aurora for that matter) connect this pin to ground.
Pin A11, Old CLKCPU, New CLK:
This may or may not contain the CPU clock, and should be considered optional (this is still open to discussion). In any case it would be nice to have a clock of some sort, but it is actually fairly impractical to guarantee it to be the original 7.5MHz clock. It should certainly NOT be expected that bus signals run synchronous with this clock if it is provided.
Pin A12, Old R, New Reserved, NC: (ERROR: marked as GND)
The pinout contains an error here, this pin is considered reserved, and it's function is open to discussion, as long as one requirement is satisfied: it must be an output from the motherboard.
There is no need to provide an extra ground pin here as pin B10 is sufficiently near.
Pin B13, Old CSYNCL, New /RFSH: (marked as CSYNC)
The function of this pin is not completely compatible with the old bus but does provide a similar signal, it outputs a negative pulse from the motherboard, with a frequency that will most likely be 16.384kHz instead of the original 15.635kHz on an non-US QL. The Aurora actually provides a 16.384kHz signal here. It is open to discussion if it makes sense for this pin to be mandatory, however, one should keep in mind that having a medium frequency timing signal has it's benefits. Since some sort of RTC will likely be present on the motherboard, it is simple to get this signal from it's 32768Hz crystal. Also, if a fast poll interrupt is implemented, it will likely be derived from this signal. The reason it is marked /RFSH is that the GC and SGC use it to trigger refresh cycles for their on-board RAM, but the name can be changed as there is no sense in connecting either the GC or SGC onto this bus.
Pin B15, Old VSYNC, New POLL: (marked as VSYNC)
The function of this pin is not completely compatible with the old bus but does provide a similar signal, it outputs a positive pulse from the motherboard, with a frequency of 50Hz. This pin may well be considered mandatory as the signal is the source of the QL's Poll interrupt and is needed for the OS to work.
Pin B16, Old VPAL, New GND:
This pin may perhaps only have been used by the QEP III programmer, and also by internal interrupt acknowledge hardware. Since it is expected that the motherboard will handle interrupt acknowledge internally, and since there is no need for it to be seen on the bus, this pin has been redefined as a ground pin connected to the motherboard gorund plane, in order to increase signal integrity. However, peripherals designed to also work on the standard QL should leave this pin open. It is also possible for the designer of the peripheral to provide an option to connect the pin to the ground plane of the peripheral if it is only going to be used on the new bus.
Pin B17, Old G, New Reserved, NC: (ERROR: marked as GND)
Pin B18, Old R, New Reserved, NC: (ERROR: marked as GND)
The pinout contains an error here, this pin is considered reserved, and it's function is open to discussion, as long as one requirement is satisfied: it must be an output from the motherboard.
Pin B23, Old ROMOEH, New Reserved, pull-down (currently marked GND)
This pin carries the ROM select output (same as on the ROM slot) on the original QL motherboard and Aurora. It's use in the new spec may be open for discussion, however, the pin must be an output from the motherboard. At least a pull-down resistor of fairly low value should be used, to make the pin compatible with peripherals that are expected to run also on old QL systems and want to use this pin. It is not necessary to connect it to the ground plane directly as there are plenty of ground pins nearby.
Pin A25, Old DBGL, New /FTACK, now labelled /WBM and should be changed to /FTACK
This pin was actually not used in old QL systems, but has a pull-up on the motherbooard. Aurora re-defined it as a Fast Transfer ACKnowledge signal, and generates it when an access is made to an area of the Aurora memory map that supports bus speeds much higher than that of the original QL bus spec. The purpose of the signal is similar to /DTACK (or old DTACKL), it is used to indicate to the CPU that the current bus cycle should end. The difference is that it should bypass any circuitry that the motherboard uses to provide speed compatibility with the old motherboard (mostly to cater for the behavior of the 8301 ULA). Using this signal instead of /DTACK should run the bus at it's fastest supported speed. This signal is optional for 8-bit bus mode but the pin should have a low value pull-up on the motherboard. The signal is mandatory in wide bus mode and is used as a wide bus mode transfer acknowledge signal.
The above changes also reflect on the bus layout for the wide bus modes, but only with respect to labeling and function of the following 3 pins:
Pin B5, ASL (Labelled ALE for wide bus modes)
Pin B9, /WTRQ
Pin A25, /FTACK
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