Exactly what I said. The reference to length was re the original motherboard that has no ground plane.Peter wrote: Nasta: The HF return path length is not what matters for the inductance, but the area encircled by it (and the signal line).
ISA (16-bit) has a few more ground lines interspersed, and the empty area is actually a bit smaller due to vertical connectors being used on a motherboard with 4 layers and decent buffering, not like the QL. Still it runs at about max 2x the speed legally and when the 16-bit extension is used - so it's not a huge improvement.If both PBCs have decent ground planes (and I don't see why there would be a large hole in those planes) even a wide connector with far GND pin opens only a small area, as long as it is not deep. For QL style signals I would not consider the connector as deep.
Anyway, the area, assuming you use SP0..3 as ground is about 21 pins long but it's also wide enough to not be simply dismissed. Two right angle connectors are used which makes every mating pair of pins a small half-turn inductor and also lengthens the horizontal path through the conenctors. Although the ground plane might well wrap around the connector pins, it could just as well end right where row c would be on both sides of the mating pair. The width comes to around 2.5cm or so. Not too terrible if you look at a single signal in isolation, but because signals are central and grounds (and I am including Vcc if it's properly decoupled) are on the outside, most of the loops co-incide especially for the the signals in the middle, and they interact to a falling degree with the signals nearer the edges of the connector. Things are slightly worse if SP0..3 are not used as grounds, extending the length of the cut-out by 1 cm. Even that is not much of a problem assuming regular QL signals - but here we are talking about extending the connector and running it potentially much faster, and I'm not talking higher clock rates. Today's components even if ran at QL clock rates are faster, and not by trivial amounts, so in many cases the bus was already ran faster. The edge rates are a problem, even the most humble HC chips and GALs will trample old style TTL in thisrespect, not only are edges faster under normal conditions (5V, room temp - more likely since they do not generate lots of heat), the output impedance of the outputs is lower so even less matched to the unpredictable characteristic impedances of the lines.
The example I made was to show that even if everything was done ideally given the current layout (i.e. proper ground planes on both ends) there is an underlying fundamental problem that limits what you can do - and in realistic cases it can get worse.
The point being, IF a 3rd row is added for any reason, it must address this problem especially if it adds signals - more loops, more interaction - and with a 3rd row, an even bigger opening in the ground plane. Reasoning out a multiplexed protocol extension was done to show that a non-nultiplexed one BARELY gets you very few extra ground pins - and it's questionable if that should make it run reliably at anything more than present speed, though with a wider bus.
To conclude, the current layout can be expanded in a useful manner even if only a few lines are used differently. Perhaps only one ground pin can be added (at the location of VPAL - better one than none), and it's use would be optional - if a peripheral is designed to also run on the regular QL, it should leave this pin unconnected. 2-row peripherals specifically made for this new J1 would put a ground plane connection on VPAL.
It is important to note that this implementation would cater for regular style QL hardware running at QL speeds or slightly higher and this assumes producing the signals with slow hardware or conditioning them to appear that way if produced by quick hardware. Clearly this is not always possible any more even with legacy boards. Replace an old EPROM with a CMOS one and already it's a different story.
For more speed (and especially if a wide bus is included in the deal) - and note, I am talking edge, not clock rates here - proper ground plane extension through the connector must include more than just one extra ground pin. Aside from replacing the connector entirely or changing the layout completely, a third row is the obvious solution, and would be required tu run wide or fast hardware optimally.
The simplest proposal is a third row with ground pins - from direct experience, one ground pin in every 6-pin 3 row 2 column group will do the trick to well in excess of 100MHz for straight connectors, perhaps somewhat lower for right angle (keep in mind a mating pair of right angle connectors presents half a turn of an inductor for every single pin!). However, this only gives us 16 usable extra pins. Even going one ground per each 3x3 group gives us 21 pins for signals, still not sufficient. So, that's why I thought it a good idea to do a multiplexed option, which also uses less pins hence less power and less problems.
The ideal 3-row version would be ground on the middle row, but since that's not compatible, we go for ground in either top or bottom row. In theory, bottom row has some advantages as the orientation notches align between 2 and 3 row connectors that way, but it's mechanically problematic as the 2-row board does not align in height so it's a real temptation to plug it into the wrong 2 rows. At one point I though up a sort of combination of right angle and straight pin 3-row with short straight pins in the bottom row, so a PCB would be wedged between the mid and bottom rows, but this is really tricky to do and solder, and then the bottom layer of the PCB would have to be routed through vias to a mid layer ground plane. So, it went back to the top row being extra. This is still easy to extend onto a backplane.
Running a mixed bag of new and old peripherals on such a system will of course result in slower attainable speeds (which is one reason why there were provisions to have the speed chosen by the user!) but the idea is to eventually replace the old with the new (perhaps way too optimistic but at least that's the theory).
The purpose of full backwards compatibility would actually be to enable development using existing peripherals initially, but with the idea to eventually replace them with new ones. These could perhaps run faster on this extended bus but that would largely be a side effect. Also very simple peripherals (short lines from J1 to the hardware on the board) could still run reliably with a regular 2-row, and such could be designed to also work on regular QLs.
All that being said, given what is planned to be included onto such a board, there is simply no sense in connecting some legacy peripherals to it at all, so consequently no sense in attempting to produce a new bus specification which is also 100.000% compatible with the old (nevermind that the old is not 100% compatible with the old
). For instance there would certainly be no sense in connecting a GC or SGC, designed to replace the on board CPU and add RAM, to a system that already has a faster CPU and more RAM. Ditto for extra RAM on an 8-bit bus, maxing out to a total of 896k, added to 16 meg or more RAM that also happens to run 20 times faster. However, it does make sense to add simple 8-bit peripherals including their on-board ROMs at least initially. One could argue that adding a floppy controller, parallel port, mouse etc on board is sensible, but take a look at where computing is going - no floppies (indeed no hard drives - flash based media instead), no parallel ports, no mouse and keyboard, instead there is USB. So, it stands to reason that a 'IO pack' board on J1 will eventually get replaced by a more modern one, while the CPU and RAM core will not.
I'm curious wether it cures the SGC related instabilities with QL-SD. 
Even if that was a Q60 detail, I would not remember anymore, let alone the QL.
Standby alert