lliont wrote:In the beginning I did the 8 cycle (of the 7.5Mhz clock) refresh for the non visible lines and tested the speed vs the ULA and for a simple basic program loop the time it took for the cpld was about 1' 17" vs 1' 15" for the ULA.
Then I reduced the 8 to 4 cycles for the non visible lines and the test took 1' 15" for both.
These tests where done with the memory upgrade installed to 832K.
Without the upgrade the times where larger but similar results, 1' 41" vs 1' 38" the first case and both 1' 38" the second.
So I think in my version of the ULA they had already reduced the refresh cycles at the non-visible lines unless I missed something I'll check again.
That is very interesting, for the non-visible lines it enough to just generate RAS low, both CAS lines stay high. It also means the length of the cycle can be halved like you did. On my version of the ULA it just continues reading data from RAM but does not display it (rolls around to the start of the screen area).
There is one more trick that offers extra improvement.
Refresh only looks at the row address and the ULA internal address lines presented to the RAM as row address are A2, A3, A4, A7, A8, A9, A10, A11.
Note that A5 and A6 are missing, this is because they are given as the low nibble of the column address together with A0, A1, this is done so the ULA has access to these address lines to decode it's mode setting register when the CPU is accessing IO space, and also to properly implement page mode reading of 4 consecutive bytes of data.
However, this also means that the same group of 8 consecutive refresh addresses will appear 4 times in a row in the invisible lines (because column address is ignored for refresh). The ULA normally reads 32 blocks of 4 bytes for the visible lines, it will also do 32 refreshes per invisible line, but only the first 8 are enough as the remaining 24 just repeat the first 8 addresses 3 more times. Disabling the repeats frees up a good number of cycles for CPU use.