CPLD replacement for ZX8301

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Nasta
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Re: CPLD replacement for ZX8301

Post by Nasta »

lliont wrote:
RalfR wrote:What I haven't really understood: How have you read the contents of the Ula to know, what it is doing?
I studied Nasta's description of the ULA. It's totally accurate and I mentioned that at my fb post. Nasta is great, respect.
Thanks,
I wonder if it is possible to do a few small improvements when using the larger CPLD, like 4 screens (changing the behaviour of CAS0/1 when reading video), and perhaps some speed improvements (freeing some cycles in the display lines that are not used for actual pixels). Also... just an extra pin that outputs the flash bit which could then be used as a 16 colour mode?
I would definitely go for the speed improvement... completely transparent. Not much but it's one of those 'lets make it right' things now that they are done again :)


lliont
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Re: CPLD replacement for ZX8301

Post by lliont »

I will try some things with the bigger cpld, I have rewritten this one so many times trying to fit the flash bit and I don't know the reprogramming limit.
The cpld has many unused pins, one could be used as "brightness" and this could be an option enabled by a jumper.
Or an unused bit from the ZX8301 internal register could enable/disable it but then software could mess with it.
With a much bigger cpld using a bigger buffer maybe more cycles from video could be freed.
We'll see.


ones' complement
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Re: CPLD replacement for ZX8301

Post by ones' complement »

lliont wrote:... I don't know the reprogramming limit.
100 times :(
MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times.


lliont
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Re: CPLD replacement for ZX8301

Post by lliont »

thanks, If I haven't pass it already I think I am close, next time I'll count :)


lliont
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Re: CPLD replacement for ZX8301

Post by lliont »

In the beginning I did the 8 cycle (of the 7.5Mhz clock) refresh for the non visible lines and tested the speed vs the ULA and for a simple basic program loop the time it took for the cpld was about 1' 17" vs 1' 15" for the ULA.
Then I reduced the 8 to 4 cycles for the non visible lines and the test took 1' 15" for both.
These tests where done with the memory upgrade installed to 832K.
Without the upgrade the times where larger but similar results, 1' 41" vs 1' 38" the first case and both 1' 38" the second.
So I think in my version of the ULA they had already reduced the refresh cycles at the non-visible lines unless I missed something I'll check again.


Nasta
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Re: CPLD replacement for ZX8301

Post by Nasta »

lliont wrote:In the beginning I did the 8 cycle (of the 7.5Mhz clock) refresh for the non visible lines and tested the speed vs the ULA and for a simple basic program loop the time it took for the cpld was about 1' 17" vs 1' 15" for the ULA.
Then I reduced the 8 to 4 cycles for the non visible lines and the test took 1' 15" for both.
These tests where done with the memory upgrade installed to 832K.
Without the upgrade the times where larger but similar results, 1' 41" vs 1' 38" the first case and both 1' 38" the second.
So I think in my version of the ULA they had already reduced the refresh cycles at the non-visible lines unless I missed something I'll check again.
That is very interesting, for the non-visible lines it enough to just generate RAS low, both CAS lines stay high. It also means the length of the cycle can be halved like you did. On my version of the ULA it just continues reading data from RAM but does not display it (rolls around to the start of the screen area).

There is one more trick that offers extra improvement.
Refresh only looks at the row address and the ULA internal address lines presented to the RAM as row address are A2, A3, A4, A7, A8, A9, A10, A11.
Note that A5 and A6 are missing, this is because they are given as the low nibble of the column address together with A0, A1, this is done so the ULA has access to these address lines to decode it's mode setting register when the CPU is accessing IO space, and also to properly implement page mode reading of 4 consecutive bytes of data.
However, this also means that the same group of 8 consecutive refresh addresses will appear 4 times in a row in the invisible lines (because column address is ignored for refresh). The ULA normally reads 32 blocks of 4 bytes for the visible lines, it will also do 32 refreshes per invisible line, but only the first 8 are enough as the remaining 24 just repeat the first 8 addresses 3 more times. Disabling the repeats frees up a good number of cycles for CPU use.


lliont
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Re: CPLD replacement for ZX8301

Post by lliont »

I just can't explain why even if I think I removed the extra refresh cycles I don't see a change in speed.
Something I am missing probably so don't take the conclusion of the last post also as a fact. I have to find out why and I am at the size limit so can't do much at the moment.
At least it works fine, haven't seen any problem after hours running.


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Re: CPLD replacement for ZX8301

Post by bwinkel67 »

ones' complement wrote:
lliont wrote:... I don't know the reprogramming limit.
100 times :(
It's interesting...I saw the data sheet on one an Altera MAX 2 and it states minimum of 100 writes, though on the particular thread I saw that on it was interpreted as meaning "you get that many but be cautious after more." Does it use the same type of flash memory as an FPGA? I only ask because on a another thread I saw a range of 10K to 100K for those being reprogrammed. Are they fundamentally different in that regard...the little that I know on this topic, I understand that for FPGA's you need a specialized programmer but for CPLD's you don't. Just curious.


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bwinkel67
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Re: CPLD replacement for ZX8301

Post by bwinkel67 »

Another off topic question here...sorry for the tangents. Someone just sent me a replacement ULA for my Spectrum. That one was developed by Charlie Ingley. I have read before how there was little documentation on the QL's ZX8301...is that true for most specialized ULA's? It's pretty fascinating the reverse engineering work that Theodoulos and Nasta had to do to get a workable prototype. Did Charlie have to go through the same process? I wish I knew more about hardware engineering (certainly want to learn more) to understand that...I'm more in the software realm :-/ In any case, kudos to that hard work in getting there.


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Re: CPLD replacement for ZX8301

Post by lliont »

With fpga is much easier, they have ram that can hold temporarily the program so you can test and debug as many times as you want and the final program is written at an external flash chip that fpga reads when it boots.


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