SMSQE in MisTer

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Tinyfpga
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SMSQE in MisTer

Post by Tinyfpga »

I am interested in Marcel Kilgus's SMSQ/E on MiSTer project but his webpage does not make it clear (to me) what one has to buy/do to build it. What is the maximum display resolution of his design and does it use HDMI for output?
I see that the FX68K core is written in SystemVerilog does that imply that the rest of the design is also written in SV?
Is the system portable, ie. can it run in any fpga large enough to accommodate it or is it dependent on the MiSTer hardware?

I recorded Marcel's recent talk on m68k including the after-talk Q&A but I stopped the recording just as he mentioned his FPGA skills, which he claimed were limited. SMSQ/E in FPGA is a remarkable achievement for someone with limited skills!

I "Googled" MiSTer and found that it is based on Terasic DE10-Nano Altera/Intel Cyclone V SoC experimenter's board which, strangely, is cheaper to buy (76 pounds) here in Switzerland than directly from Terasic.
sbyford_210303_4461_0014.0.jpg
From GitHub:-
MiSTer utilizes a readily available FPGA board called the 'DE10-Nano', which connects to your TV or monitor via HDMI video out. It can additionally be expanded with various add-ons (such as a USB hub, SDRAM, audio and VGA out).
The MiSTer software/OS itself is freely downloadable, and anyone is welcome to contribute to its development. In fact MiSTer relies on the contributions of many developers for the various systems (known as 'cores') it replicates.

and

FX68K 68000 cycle accurate SystemVerilog core Copyright (c) 2018 by Jorge Cwik fx68k@fxatari.com

FX68K is a 68000 cycle exact compatible core. At least in theory, it should be impossible to distinguish functionally from a real 68K processor.
On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max effective clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance.
The core is fully synchronous. Considerable effort was made to avoid any asynchronous logic.

Written in SystemVerilog.
The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal.
It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented.

I also found the following info on the Internoodle (as a friend of mine calls it)

https://www.theverge.com/22323002/miste ... e-early-pc
https://www.terasic.com.tw/cgi-bin/page ... 67&No=1046


Derek_Stewart
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Re: SMSQE in MisTer

Post by Derek_Stewart »

Hi

I had asked the question as well what is the best configuration for the Mister QL.

But I remembered I have already asked the question previousily, in this message thread:

viewtopic.php?f=2&t=3475&p=36703&hilit=mister#p36706

Read the complete thread may help.

I am saving up for a DE10 Nano...


Regards,

Derek
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desin
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Re: SMSQE in MisTer

Post by desin »

hello Tinyfpga
in addition to the DE10.Nano board you need :
build or buy the SDRAM Module https://github.com/MiSTer-devel/Main_Mi ... DRAM-Board
build or buy the IO board https://github.com/MiSTer-devel/Main_Mi ... i/IO-Board
you can use a usb Hub or bulid/buy one https://github.com/MiSTer-devel/Main_Mi ... hter-board

i can recommend this kit https://www.antoniovillena.es/store/product/kit-mister/

Greetings from Switzerland
Markus


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NormanDunbar
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Re: SMSQE in MisTer

Post by NormanDunbar »

tinyfpga wrote:SMSQ/E in FPGA is a remarkable achievement for someone with limited skills!
I've said this before, and will definitely say it again, Marcel has a brain the size of a planet. And, I'm not kidding. He wrote QPC at the age of 14 I believe.

Cheers,
Norm.


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mk79
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Re: SMSQE in MisTer

Post by mk79 »

NormanDunbar wrote:I've said this before, and will definitely say it again, Marcel has a brain the size of a planet. And, I'm not kidding. He wrote QPC at the age of 14 I believe.
That would explain my headaches :-D Yes, I was about 14 and didn't get out much :-D

Regarding MiSTer, the I/O board is not strictly needed anymore, the SDRAM board is a must however. The release version does only the standard 512x256 resolution, but rescaled over HDMI, so can be used with pretty much every monitor and TV. Maybe someday there will be a 1024x768 version, but currently I lack the time to get anything done.


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Re: SMSQE in MisTer

Post by NormanDunbar »

When I was 14 I didn't get out much either, but I didn't write a full blown emulator! Mind you, when I was 14 the ZX81 was still 7 years in the future. I was helping my dad fix engines.

Cheers,
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Re: SMSQE in MisTer

Post by mk79 »

Well, that's hardware problems then, a good skill to have, too :-) I can only solve software problems. Lucky for me, most things eventually turn into software problems. Electronics problems can often be solved using Microcontroller and FPGAs and now that I have a 3D printer even my mechanical problems can be solved by writing some lines of code in OpenSCAD :-D


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Re: SMSQE in MisTer

Post by NormanDunbar »

I left school at 17 to start work as a Honda motorbike mechanic onthe basis of what my dad taught me, plus, my reading Motorcycle Mechanics magazine every month. When the shop closed three years later, I was then employed as a Yamaha outboard motor/Volvo Penta marine diesel engineer and fibre glass boat builder, for another 3 years.

Then I bought a ZX81...............

Cheers,
Norm.


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Tinyfpga
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Re: SMSQE in MisTer

Post by Tinyfpga »

The last four posts between Marvin and Norm read like the beginnings of something like the 1967 "Good old days" sketch. Link below for those that do not know it.

https://www.youtube.com/watch?v=VKHFZBUTA4k

Anyroad, I thank MK for the information. I think I will wait for a high resolution version of his MiSTer "QL" core.

Unless it is a secret, is there any chance of MK (or anyone else) expressing a view on my other questions, namely:-

Is the core written in SystemVerilog?
Is the system portable, ie, could it be used in any FPGA large enough to accommodate it or is it hardware dependent?
and
What determines or limits the performance of FPGA 68000 systems?
What do you think of using SRAM as main memory?
- SMSQE seems to work perfectly well in 8MBytes . CY62187EV30 64Mbit 55ns SRAM costs a mere 56CHF.
What do you think of the 68080 core?
What do you think of the RISC-V core?
Last edited by Tinyfpga on Wed Oct 06, 2021 10:39 pm, edited 1 time in total.


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mk79
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Re: SMSQE in MisTer

Post by mk79 »

Tinyfpga wrote:Anyroad, I thank MK for the information. I think I will wait for a high resolution version of his MiSTer "QL" core.
You might be in for a long wait then...
Unless it is a secret, is there any chance of MK (or anyone else) expressing a view on my other questions, namely:-
The source code is open, difficult to hide a secret in it.
Is the core written in SystemVerilog?
That and Verilog.
Is the system portable, ie, could it be used in any FPGA large enough to accommodate it or is it hardware dependent?
Difficult. It depends on the MiSTer framework for menus, disc access, video output, etc.
What determines or limits the performance of FPGA 68000 systems?
The speed of the FPGA chips and the skill of the implementer.
What do you think of using SRAM as main memory?
Easier.
- SMSQE seems to work perfectly well in 8MBytes . CY62187EV30 64Mbit 55ns SRAM costs a mere 56CHF.
As long as you don't have much video resolution/colour depth that is.


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