68008 and bus request at reset / startup

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Pr0f
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68008 and bus request at reset / startup

Post by Pr0f »

I tried searching in several of my Motorola datasheets and books for the 68K series Microprocessors, but information about how the processor reacts to the Bus Request signal at start up is non existent (that I could find)

Does anyone know of any official sources for how this signal is dealt with on startup / processor reset ?

I am assuming it works as the GC / SGC both just tie this line to ground on the edge connector, just be nice to see that in documentation if it existed


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Re: 68008 and bus request at reset / startup

Post by tofro »

The hint is in the manual:
Bus requests can be issued at any time during a cycle or between cycles.
"any time" means to me that it includes /RESET going high.


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Re: 68008 and bus request at reset / startup

Post by Pr0f »

tofro wrote:The hint is in the manual:
Bus requests can be issued at any time during a cycle or between cycles.
"any time" means to me that it includes /RESET going high.
that was my assumption as well - I did wonder if this particular edge case had been documented at all by Motorola.

The first 2 operations after coming out of reset are to fetch the Stack pointer and program counter vectors (in supervisor program space) and then start executing the code at the program counter address provided - so it's kind of a question - does that fetch still happen or does bus request happen before even the first instruction proper is executed?


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Re: 68008 and bus request at reset / startup

Post by tofro »

It can only wonder where this could be relevant:

Any external bus access may only happen after BUS GRANT goes low - And whatever the CPU does between BR and it activating BG can only be internal to the CPU's state - it will properly finish all cycles it's been doing (if any), then hand over the bus ("larger" 68k CPUs than the 68008 also have the capability to reacquire the bus on their own if the Bus Grant is not properly acknowledged by the requestor - but the 68008 doesn't have a BGACK pin).

For the GC or SGC that behavior is entirely irrelevant, however: The 68008 CPU will never come back to life after its first few (if any) baby steps anyhow. I understand you're asking for the if any - but don't get the relevance.


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Re: 68008 and bus request at reset / startup

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The 52 pin 68008 does have a BGACK pin.

The question was related to some ideas / musings on using a technique that's well used elsewhere of counting the first few AS strobes to allow a ROM to sit in place of the RAM at the first locations in memory while the first 2 vectors are grabbed from there, and thereafter RAM would be addressed there.

So the question has some relevance on how that might work or not during the reset processing.

So not relevant to a stock QL, as that has ROM in the memory map from address 0 and that never changes.


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Re: 68008 and bus request at reset / startup

Post by tofro »

Pr0f wrote:The 52 pin 68008 does have a BGACK pin.

The question was related to some ideas / musings on using a technique that's well used elsewhere of counting the first few AS strobes to allow a ROM to sit in place of the RAM at the first locations in memory while the first 2 vectors are grabbed from there, and thereafter RAM would be addressed there.
That's definitely a setup that has not much to do with the current GC/SGC one. If you want to make sure the CPU does its first baby steps undisturbed , there must be a means for the CPU to gate a BR signal (a simple NAND controlled by a port bit would do the trick) rather than BR hardwired to GND.


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Re: 68008 and bus request at reset / startup

Post by Dave »

There's at least three different behaviors, tied to mask revisions.

The early masks (usually ceramic ICs) go through the first attempted instruction and bus grant before starting the next instruction.
Some masks start CPU operation and get to the end of the first clock cycle, then BERR twitches and the cycle stops and BG asserts. I believe this was an errata.

Later devices (usually plastic, and most PLCC it seems) don't start the first cycle and immediately issue the BG. The HC and EC/SEC000s behave this way too.

None of the masks revisions get past the first instruction.


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Re: 68008 and bus request at reset / startup

Post by Pr0f »

Thanks Dave

It would be interesting to see what's defined as the 1st instruction, as from the reset timing diagram - the 1st full cycle is internal, and the next 4 cycles retrieve the 4 words that make up the SSP and the PC - then the 6th cycle is the 1st actual instruction to be processed. Do you know if the 68EC/SEC parts are static and can be clocked slowly? I know the nmos parts have a minimum clock requirement, so that won't work for them.


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Re: 68008 and bus request at reset / startup

Post by Dave »

The 68EC000 is not static, but the 68SEC000 is, and can be clocked down to nothing for a period. Note that the halting of the CPU will result in loss of state after a short period unless the STOP instruction has been loaded in supervisor mode, in which case the CPU can be halted indefinitely.

The 68SEC000 handles BR/BG nicely, typically after two clock cycles.

The (S)EC devices do lose some interrupt options.


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