in the past, ethernet for the QL has been discussed here quite a lot. Now that Martin's ethernet driver for the Q68 has arrived, see https://qlforum.co.uk/viewtopic.php?f=3&t=3578, I think it is a good time to provide information and schematic sources here to help others building the equivalent hardware for an original QL. I think it has become practical now - unless all who are interested in ethernet have or want a Q68 anyway.
I chose the CP2200 ethernet controller for the Q68, because it also interfaces very easily to the original QL bus. Firstly, all signals are 5V tolerant. Secondly, it has a non-multiplexed 8 bit data bus, requiring no serialization. Thirdly, it requires only address decoding, no further logic to interface directly with the QL bus. Please find below the priciple schematic, based on the working and tested Q68 circuitry:
- The CLKIN signal has to be a 20 MHz clock.
- The /ETH_CS signal needs to be generated by an address decoder, which is specific to the project into which ethernet is integrated. For a stand-alone extension this could be a GAL.
- The /ETH_IRQ signal has to generate a level 2 interrupt for the QL. There is a specialty here, inasmuch the CP2200 activates the interrupt line on power-up. If possible, it should be deactivated by software before interrupts are allowed for the CPU. If this is not desired, as it requires a (minimal) ROM change, a hardware register should be added in the external logic which gates this signal.
All the best