The Sinclair QL Forum

Looking around the clock circuit of the 8301 the picture shows the capacitor is not ideally placed and the joint has a lot of flux I think giving the brown colour. The clock signal is very sensitive compared to others I have been involved with so I put the capacitor in its correct position flat on the board improving the joint at the same time. It didn't make the QL work but things appeared to have changed again. The CAS1L signal is now working where it seemed to be stuck high before. The scope measures 15 MHz now and there are a lot more colours in the screen like darker blues and more vivid red. Don't ask me what is going on I am just reporting what I see but it seems incredible the QL ever worked.
I suspect my home made ROM containing Minerva still has a dodgy connection somewhere and might be a problem I have added to the mix. Since the IC33 original ROM definitely is dead maybe if I get my replacement working the whole QL might work given the above improvement.

Do all capacitors on your board look like a resistor?

Edit: OK, seems to be the norm with Issue <6 boards.

Are you using the EPROM directly? EPROM chip select is active low.

mk79 wrote:Do all capacitors on your board look like a resistor?

I see you answered this yourself. I don't remember seeing capacitors with resistor type markings that are very confusing they are normally like the yellow ones between the RAM chips.
I have fixed my home made ROM board I think because everything has gone more stable and it looks like it is just the RAM now. The screen and background always come up the same with the same background.

mk79 wrote:- The first value you see on screen is the 32-bit value written, the second the one read back. So your D0 bit is stuck high.- If bit 0 was low in the displayed picture this would point to IC21. Your picture is pretty bad quality to tell much, but it looks like bit 0 is stuck high in the displayed picture, too (the white stripes). Meaning that either IC1 and IC9 are both faulty or, more likely, that one of the chips or something else pulls the line high. Basically it boils down to IC1, IC9, IC21 and IC22. Or some other bridge bringing D0 high on the ULA bus side.

Yes I thought bit 0 was the problem but after looking at the numbers I have seen it change state so it isn't stuck. What appears to be happening is it depends on what value was previously set. I am not 100% sure but it looks like if it does get changed it is held so I had a look at the selection signals on the buffer. The R/W pin 1 is working but I am not sure about the !OE from the HAL chip. It has a regular 25 nS pulse down. Other pins on the HAL have loaded rise times like a capacitor charge up curve that takes over half their pulse width to get over 80% that I would not be happy with if I had designed it. Any suggestions on verifying the HAL chip or what to next would be appreciated.

Dave wrote:Are you using the EPROM directly? EPROM chip select is active low.

I am using the home made EPROM pictured here
viewtopic.php?f=2&t=3256
that now has Minerva in it instead of Tyche.

An interesting anomaly that might give a clue to the fault is if I press the reset button lots of times I have seen 2004, 2008, and 200C as the faulty address instead of the normal 2000. It appears as though if I press the reset button fast the different addresses occur more often but it might just be that it is a bigger sample in a shorter time. If Minerva is getting to higher addresses doesn't that mean all the memory must be working but has a timing problem that backs up the fact that bit 0 is not stuck since it has assumed both 0 & 1? Also why would the higher addresses be 4 apart on each failure that must point to a particular address bit when the timing failure occurs?

What did you see when you checked the power to the DRAm area? Was it nice and smooth, or dipping? What about at the 8302?

The inconsistency of this is similar to a QL I repaired many years ago where the DRAM wasn't refreshing properly, and it turned out to be a power/bounce problem.

Dave wrote:What did you see when you checked the power to the DRAm area? Was it nice and smooth, or dipping? What about at the 8302?

I didn't look at the power rail at different particular points but I did look to see if was there. It was glitchy and you could see small square waves on the rail but it was all less than 250mV so nowhere near the logic levels. I will have a look on the chips like you suggest. What about the slow edges on my HAL chip that look like capacitor charge up curves rather than square waves as if they are heavily loaded or is that normal?

Done more poking around with the scope and the power rails on all the RAM chips are probably the best bit of the whole box. The HAL chip is the thing that does bother me but it might be perfectly normal I don't know. The pictures show pins 15 & 19 the OE and DTACK signals respectively. I would say both signals are not what I call good but maybe they are acceptable on the vintage QL and normal. The 25nS is the rest state of a regular pulse that becomes 250 nS for an active signal like the Minerva memory changing on the screen. As for the DTACK I am assuming the shorter pulses are the inactive state and the longer one is active. Could someone enlighten me if they are good enough or not?

DTACKL looks normal. Not sure about OE. I've measured these on my QL for reference, you have much more ground noise, but could be that the Samsung QLs were better in this respect.
DTACKL:OEL: