Issue 6 VM12 & resistors confusion

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Ruptor
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Issue 6 VM12 & resistors confusion

Postby Ruptor » Thu May 14, 2020 2:30 pm

I am sure this has been discussed before so can someone point me to the answer. The wire to the two resistors on top of the 8302 came off so I looked at the circuit to find which pin it was on and this is when the confusion set in. The circuit already has two resistors R107 & R108 of 33K under D30 to the right of IC30 on the circuit. Then there are two 0R resistors labelled R102 & R103 and what I assume is the added resistor mods also called R102 & R103 connected to VM12. Even more confusion occurs because pin 1 of IC25 the MC1488 is -12V not VM12 and I can't see the inductor L5. I belled out IC36 next to the reset switch and pin 1 of IC25 and they are the same point so -12V and VM12 nets on the circuit are shorted together so appear to be the same net but they might have the inductor in between if it exists.
Can anyone enlighten me to the true circuit ?


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Re: Issue 6 VM12 & resistors confusion

Postby martyn_hill » Thu May 14, 2020 4:23 pm

Hi Ruptor

Yes, the schematic in common use remains a little inaccurate in some regards (most notably, that the Iss6 schematic still shows the ZX8302 as attached to the internal RAM/8301 Data bus, whereas it is in fact connected directly to the CPU side of the bus). Out of interest, which copy are you referring to today?

As far as your specific question is concerned, the schematic is actually correct in that the common-end of the two 33kOhm resistors needs attaching to the -12V rail - otherwise known as 'VM12' - i.e. Voltage Minus 12 - which is most readily available at pin#1 of IC25 - the quad Line-driver, as you've observed.

As far as I'm aware, no production issue boards actually included the 33k resistor mods directly on-board, even though the schematic might lead you to believe that they were pre-fitted. I should ask my brother sometime, who used to work at Thorn-EMI when they were still maintaining Sinclair's boards...

L5 still appears on my boards - over on the far left near the MDV expansion connector.

My experience shows it seems to make little difference to MDV performance if left detached, but I still apply/maintain this mod on my boards as a matter of course. In fact I typically re-build this mod on the _underside_ of the board whenever possible, so that I can easily switch-out the 8302 during maintenance...


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Re: Issue 6 VM12 & resistors confusion

Postby tofro » Thu May 14, 2020 4:30 pm

Most of the issue 6 mods were introduced to stabilise microdrive performance. If you're not using the mdvs (highly likely these days), there's little point in adding the mods. I have removed all of them on my issue6 boards, without any noticable compromise on stability.

Tobias


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Re: Issue 6 VM12 & resistors confusion

Postby Ruptor » Thu May 14, 2020 5:25 pm

Thanks guys. I think it is the issue 6 circuit in the service manual 1.18. Something has changed after soldering the wire back all the random screen writing has gone on both the original ROMs and my replacement ROM board with Tychie image shown here.
viewtopic.php?f=2&t=3256
Strange that the two resistors R107 & R108 are on the schematic and yet didn't end up on the board but the mod was added to the schematic. It is as if they didn't know they were already there on the schematic at the other end of the lines. :?
Both the original and Tychie cause the same pale grey screen now and but they write the screen at different times. Tychie comes straight up with the screen so it must write it real quick where as the original ROMs roll up the memory clear so you can see it. I didn't appreciate that the processor was doing that I just thought the screen was rolling up trying to sync to the modulator video signal at power on. So now I know the CPU is running the code up to a point and the screen memory seems to be written to in order that implies it works but I don't know about the rest of the memory. :roll: I wonder if looking at the ROM code could tell me where it is getting stuck after it clears the screen memory?


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Re: Issue 6 VM12 & resistors confusion

Postby martyn_hill » Thu May 14, 2020 6:08 pm

Hi Ruptor

If the memory test seems to complete, but the expected boot-up screen doesn't follow, then the next section in the QDOS ROM's start-up sequence involves configuring the ZX8302 (e.g. stopping any previously running MDVs, setting the default output BAUD rate, etc.) then reading the real-time 'clock'.

I've had boards fail precisely here when there was a problem with the 8302 (usually, of my own making!)

If Minerva is fitted, then the above failure can be observed with the Minerva logo appearing in red in the bottom right (produced actually as part of the RAM test routine), but the memory/time display window in the bottom left doesn't then show-up. If plain QDOS, you would just be left with a black display (the original-style F1/F2 message not appearing.)

Can you capture a short video of the boot-up sequence (QDOS, rather than Tyche - I'm not personally familiar with its start-up sequence) and share here?

M.


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Re: Issue 6 VM12 & resistors confusion

Postby Ruptor » Thu May 14, 2020 8:54 pm

Hi Martyn
martyn_hill wrote:Can you capture a short video of the boot-up sequence (QDOS, rather than Tyche - I'm not personally
familiar with its start-up sequence) and share here?
Tyche and QDOS end up on the screen as the first picture on this thread with the black bar at the bottom that is probably not that obvious.
viewtopic.php?f=8&t=3065&start=20
The screen is clearer than the picture and is instant using Tyche but delayed on QDOS that rolls up from the bottom.
The black bar at the bottom is instant with both systems so either it is a defective memory band or it is the bottom of the screen scan.
Thanks for the idea with the Minerva ROM I shall try and burn that in my new EPROM that can hold 4 images and select it to see if red lettering is displayed.
Oh! wait a minute I thought Minerva was an OS but are you saying QDOS or the old ROMs have to be in place and Minerva in the ROM slot? I suppose I could put the original image in and Minerva above it since my EPROM is in 64K chunks and covers the ROM slot area I think but I will have to look it all up. :?
I just noticed I was calling Tyche ROM Tychie just yet more proof I am useless at remembering names. :lol:


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Re: Issue 6 VM12 & resistors confusion

Postby Ruptor » Fri May 15, 2020 5:17 pm

I stuck the Minerva IO fixed code in the next 64K block of my 8 image EPROM but it doesn't give a picture. There are two variables in play because my homemade EPROM board might not be 100%. and I won't know until I actually see it run in a working unit. :roll: I don't have a selector switch so have to solder the pins and the crappy Chinese prototype board can't take it. Fancy making prototype board that can't handle resoldering when that is the main function of that type of board. The stupid pads are very thin copper and come unstuck real easy. :evil: When I fit a switch I will be able to check that Tyche still does the same and I will put my original ROM code in another slot for comparison.
The screen sequence at the moment seems to be the blank screen like before followed by 3 seconds of what looks like red and green predominant colours on an out of sync screen that seems to be going in sequence as if a reset takes place. Not sure why faulty running code would cause an out of sync screen but maybe the address is being screwed up. Some unconnected tracks are cracked on the crap Chinese board probably from pushing it in and out of the board so there might be a crack in a vital one. :roll:


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Re: Issue 6 VM12 & resistors confusion

Postby Ruptor » Fri May 15, 2020 10:03 pm

I put the Minerva as second ROM image in my EPROM now I get the three memory address lines that have different numbers every 5 seconds or so and they are never the same after a reset. How do I read the numbers is there a manual about the Minerva memory test? At least I know the EPROM and homemade board is working. :)
The two top numbers are often 8 hex digits & the bottom number is 20000.
What does that say about the memory addressing?


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Re: Issue 6 VM12 & resistors confusion

Postby martyn_hill » Fri May 15, 2020 11:18 pm

Hi Ruptor!

So, now we are getting someplace :-)

To help you interpret Minerva's RAM failure messages, there is a simple Basic utility that came part of the Minerva software 'distribution' - of course, to run it, you'll need a working QL or emulator to-hand...

In short, however, the first long-word of hex digits is the value that Minerva thought it had written to the RAM, the second what it read back (should have matched line-1), the third, the memory address that showed this failure. '20000' in Hex is the base of RAM in the QL (at 128KB in the overall memory map - where the video-display is mapped.)

The actual values read-back can, in some lucky circumstances, help identify which DRAM IC(s) is/are at fault. The Minerva RAMFAIL_bas utility shows you this graphically. However, it only really helps if the error-bits in the values show some consistency between reboots, which is sounds like they don't...

Given the symptoms described so far, we can conclude that the ROM is being addressed correctly, CPU being clocked and running the ROM code, but that access to memory is being hosed...

That can be caused by:
A. A faulty bus-transceiver (the LS245)
B. One or both faulty Address multiplexors (LS257)
C. One or more DRAM IC failures
D. Shorts (or open-cct) on one or more address or data lines - probably 'inside' the data-bus managed by the ZX8301 ULA.
E. A faulty or on-the-edge ZX8301 ULA itself.

None of the above items would necessarily affect the ROM being accessed, as that lives on the CPU-side of the data-bus, and up until the RAM test, the only one taking any notice of the state and contents of the DRAM is the 8301 whilst it (tries to) builds its video-display.

We can also add another possible suspect - the EPROM itself. If its outputs fail to go tri-state when not being accessed (via ROMOE generated by the 8301), this will interfere with the data-lines that should be carrying the ram-test values back and forth from the DRAM during the test. Again, it wouldn't necessarily show itself until this stage during the boot-up sequence.

Keep us posted - we all love a QL-hardware mystery on a Friday night!
Last edited by martyn_hill on Sat May 16, 2020 12:24 am, edited 1 time in total.


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Re: Issue 6 VM12 & resistors confusion

Postby tofro » Fri May 15, 2020 11:55 pm

martyn_hill wrote:We can also add another possible suspect - the EPROM itself. If its outputs fail to go tri-state when not being accessed (via ROMOE generated by the 8301), this will interfere with the data-lines that should be carrying the ram-test values back and forth from the DRAM during the test. Again, it wouldn't necessarily show itself until this stage during the boot-up sequence.


Martyn,
a failed EPROM seems relatively unlikely. Any lines stuck on the data bus would most probably affect the screen display.

Tobias


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