Some time ago I designed a number of methods to add EPROM (NVRAM, actually) in to the upper 128KB area, allowing for up to 640KB (additional = 768KB total) RAM.
I have placed most of those utilities in that space, including many other DIY TK routines as well - all merged with T & EM (though the DIY TK equivalent utility would have worked as well.)
If you really have to avoid using the expansion port, as I did in one of my designs, you have to resort to some hackery. Doable, but a little bit involved - I'll describe below in case its of interest.
Ultimately, it's FAR easier to go the expansion connector approach, as long as you have one of the various bus-expanders (Dave sold a simple adapter that may meet your needs - not sure if he still has any in stock...)
In my case, I actually use a 512KB SRAM backed-up with a Varta 3.6V cell-pack and a small battery-backup monitoring/Chip Select gating IC, with the top 128KB re-mapped to the right slot in the QL memory map (at 896KB upwards.) The lower 128KB of SRAM is configured to shadow the base 128KB for Reads (Writes pass-through to the DRAM), giving a slight but significant speed increase to the lower 128K of RAM... The remaining (middle) 256KB of the SRAM IC are mapped as RAM, giving 384KB RAM altogether + 128KB for the NV portion. Sounds complicated, but works really nicely and allows for in-band/in-socket re-writing to the NV portion of the SRAM as I was continuously updating the contents! I use one of the spare IO ports of the Hermes (normal or super) to dynamically enable Write access to the upper 128KB of the SRAM (defaults at power-on to Write-protected.)
To keep my expansion port clear, I designed a daughter board that fitted in one of the ROM sockets - capturing the majority of the Address and Data signals needed.
The additional signal lines (RWL, DSMCL, DSL, DTACKL, A16..19) I grabbed from the mainboard via a 10-way (8 needed) IDC cable, soldered to the respective pins of the CPU and ZX8301 on the underside of the mainboard, routing the flat IDC cable up and over via the cut-out by the ROM port, then terminated in a 2x5way IDC plug/connector to the daughter board. Quite tidy, but physically blocks use of the ROM port, which I was not using - you could route the flat cable elsewhere to keep the ROM port clear.
A simple 16v8 GAL does the address/control decoding and generation of (tri-stated) DSCML and DTACKL when addressing the SRAM, making provision for the dynamic write-protection of the upper 128K, using the Hermes IO output to gate the WR line to the SRAM.
If of any interest, I could provide more details via PM. Its not for everyone, so wouldn't want to occupy this thread...
Last edited by martyn_hill
on Wed Mar 25, 2020 9:25 pm, edited 1 time in total.