Peter wrote:
Nasta wrote:
Have also a look at the maximum period required for /RAS. It does have a maximum (as long as it is) so it cannot be completely static. But I am sure at that rate the current consumption would be FAR lower.
Not sure what you mean - /RAS pulse width seems irrelevant, /RAS would never be active. Do you think there is a requirement to toggle /RAS if DRAM contents is never needed?
Most (though not all) 6164 family DRAM (and even to the latest parts) have (surprisingly) a limit to the maximum /RAS high spec (at least last time I looked). This suggests that it can't be completely statical. A long time ago i read the reason for this is that /RAS cycling is used to drive an internal charge pump which generates a negative substrate voltage for the RAM chip, which is not visible on the outside.
In all probability this should not mean anything since the RAM chips themselves would not be used, BUT address and data pins would still toggle levels. The problem might arise if the internals of the RAM chip expect that internal negative bias to operate the pin buffers properly, which is a big unknown. I suppose it could be tested for by looking at the data and address lines with all control signas (/RAS, /CAS, /WE) disabled and compare with the case of /RAS cycling at some very low speed (like a horizontal synch signal which has to be derived by the FPGA anywahy).
Peter wrote:
Nasta wrote:
This suggests that you would implement the entire 128k inside the FPGA?
Not necessarily. If it was a PCB for BGA cases anyway, a small external RAM should also fit. But simply spending €4..5 more for 128 KB FPGA Blockram and save the extra work is tempting. Total overkill, I know.
I suppose depends on how the internal RAM is organized. An external SRAM (128k) is cheap and actually simplifies logic as it keeps the data lines to the FPGA input only, considering that internal block RAM needs only to be written (in parallel with the external 128k), while data is always read from the external RAM.
Peter wrote:
Side remark: When Dave asked about the Q68 FPGA as a separate chip for re-use on other form factors, I was not totally opposed. I just asked for a separate discussion thread.
An interesting idea on many levels, but you are right, a separate thread is needed.
BTW regarding ROM shadowing, what would be the purpose? Ability to soft load different OSs?