3) 16 color mode. This can be done externally with some logic that has to extract a 10MHz clock from the available 15MHz, and use it to sample and process RGB. An extra control bit could also be implemented using external logic.
Dealing with some wave shaping at the Microdrive design topic, also reading a little bit about FPGA and Verilog definition language.
I have some confidence to copy the example of clock divide by `3'. Clock divide by `two' is simple pass through a NOT gate (or a diode?), that is detecting positive edge only.
Code: Select all
module clk_div3(clk, reset, clk_out);
reg [1:0] pos_count, neg_count;
always @(posedge clk)
else if (pos_count ==2) pos_count <= 0;
else pos_count<= pos_count +1;
always @(negedge clk)
else if (neg_count ==2) neg_count <= 0;
else neg_count<= neg_count +1;
assign clk_out = ((pos_count == 2) | (neg_count == 2));
The idea of divide by `3' is to count positive also negative edge. This is a simulation of in
put and output wave.
To design `16-bit' color bit VGA signal reprocessor is beyond my capabilities. But perhaps with some help I may start by pinning down all input/output signals needed.