The Sinclair QL Forum

So - there seem to be some rules about what can go where and what will co exist and what will not. A standard Qubide with Qubata ROM can't co exist with Qimsi - even if you move the address of the qubide out of the 0x0C000 address range (ROM Slot) - the device driver name and commands like WIN_USE c...

The Microdrives take their power from the 9v rail, from the power supply, which also feeds the main regulator.

If the rest of your QL has power, then the Microdrive units should also be seeing that power.

My guess would be stepper motor controller and driver...

I think this is an excellent idea Martyn! The idea of an open network that would be usable with other Micros - love it. I think it would be good to have support for 'lesser devices' - enabling support for hardware interfaces - such as LCD display module, digital I/O and analog I/O - perhaps achievab...

I've only ever seen a Q40 for sale - so the rarity value alone would mean a reasonable price tag, but then you are getting a significant upgrade to a QL! A new 68060 design would probably need to use a PCI bus, which is becoming old technology now too, unless of course you go down the route of using...

The code in the mister FPGA does just enough to 'mimic' a Microdrive interface, and provide a rudimentary seconds counter RTC, but don't be fooled - there is a lot that's not supported here - not sure if the QL network interface is implemented in the mister hardware? Certainly the serial port (trans...

As per my previous post - the OE signal on the Eprom is active low - and on the QL PCB - and hence on the ROM socket - it's active high. You will need to invert the signal with a transistor or a logic gate. Easiest would be to use a BS170 mosfet - gate to the ROMOEH signal on the QL socket, Source c...

It also makes me wonder if the 68K/OS can potentially access ROM disks at other possible ROM locations - such as at 10000 or 14000, or in the top 256K of space - from 0C0000h onwards.

Obviously dependant on any expansion cards or GC or SGC being present.

would be handy to design a ROM port plugin cartidge with a switch or jumpers and a ZIF socket - for just such experiments

The main issue from memory is that an Eprom has two pins OE and CE - these are both active low (when 0v, they are activated). On the 28 pin socket - the A15 address line is where you would normally find CE - so that will address the Eprom from 00000h to 07FFFh - which is the bottom 32K - no problem ...