The Sinclair QL Forum

Games and the KEYROW and BEEP commands also call the IPC to directly scan a key row and to start and stop sound. To my surprise, during Q68 testing, no games were found which directly access the IPC for sound. Do you know any games that do? I was at first considering to implement the IPC inside the...

While IPC comms on an original QL works based on pure polling, the Q68 PS/2 interface needs interrupts enabled for the emulation - KEYROW scans with disabled interrupts thus simply don't work on a Q68, so, games and other software that completely disable the OS won't work properly there. For clarif...

My question here would be, what parts of the 8302 (and through it the IPC) are actually used on the application level. At first glance I'd say: Realtime clock, microdrive for copy protection, and (although it makes no sense) keyboard direct hardware access in very few games. The Q68 does not implem...

Sounds cool, any chance it will run on native hardware?

Hi and welcome to the QL Forum! I hope you will receive your Q68 soon and have a lot of fun.

Eh, yes - the thing is, we re limited to A16, A17 for decoding and that means 256k total which implies a cut-down version of SMSQ/E :( I didn't mean that SMSQ/E must fit into a 8301 replacement - it would require a RAM extension anyway and could be loaded from mass storage under QDOS/Minerva. But a...

A long time ago i read the reason for this is that /RAS cycling is used to drive an internal charge pump which generates a negative substrate voltage for the RAM chip, which is not visible on the outside. I have seen a maximum /RAS high time only for similar DRAM chips yet, not the 4164 in particul...

RWAP wrote:A quick look on ebay shows some ps/2 mouse to serial port adaptors.

The adaptors I saw are passive and only work with obsolete combo mice which are also serial internally. No solution for recent PS/2 mice.

Have also a look at the maximum period required for /RAS. It does have a maximum (as long as it is) so it cannot be completely static. But I am sure at that rate the current consumption would be FAR lower. Not sure what you mean - /RAS pulse width seems irrelevant, /RAS would never be active. Do yo...

DB0..DB7 - input - RAM (and in most cases 8302) data bus, connects to the CPU data bus using a 74LS245 bus buffer. In case of a "modern" FPGA 8301 replacement with sufficient RAM, I would make DB0..DB7 bidirectional, not input. Keeping /RAS, /CAS0, /CAS1 and /WE inactive should be suffici...