The Sinclair QL Forum

I don’t think there will be very much interest in this subject unless some software is developed that makes good use of the concept - a killer app so to speak. But anyway... The documentation clearly shows that the Acorn Tube is designed around using the BBC operating system, and this extends down t...

TV standard CRT monitors just need some adjustments or modifications to the horizontal time base circuitry. Of course, this is easier said than done on most of them. *Some* LCD monitors that can handle TV standard video have nearly enough adjustments. TVs often don’t have any provision for any adjus...

I can’t answer the question of overall sales, but of the QLs that I have (five cased, and some that are just PCBs) they are a mixture of issue 5 and issue 6 boards as far as I know. But then I only got interested in them In 2011... I think somewhere on this forum I posted a picture of a QL circuit b...

How are we defining multitasking? Only the Sinclair ZX81 could be described as a very limited multitasking system because in normal (slow) mode the CPU was constantly (as far as the user was concerned) switching between running the users program and generating the serial data stream to maintain a st...

Getting back to the real question, do you want a low cost, but very high performance second processor? If the answer is yes, it makes sense to make the interface compatible with the Acorn Tube. Why? Well because the Acorn community have already developed a Raspberry Pi solution called PiTubeDirect. ...

The hardware for an Tube “interface” does not even need a DPRAM. The hardware of the second processor does all the hard work. The Tube “interface” or port is just buffered address and data busses. Plus some control lines. Like this: Address lines A0 to A2 (A0 to A6 are present on the BBC B and Mast...

The hardware for an Tube “interface” does not even need a DPRAM. The hardware of the second processor does all the hard work. The Tube “interface” or port is just buffered address and data busses. Plus some control lines. Like this: Address lines A0 to A2 (A0 to A6 are present on the BBC B and Maste...

The NMOS and CMOS Z80 microprocessors always put a sixteen bit address out on the address bus. Including during I/O and DRAM refresh operations. The Zilog documentation always specifies the lower 8 bits (A0 to A7). For some operations, the Zilog documentation also specifies the higher 8 bits. How us...

As browsing the Internet even using older PCs is now getting more and more painful, and as more and more emails contain photos, images and attachments (and most of the time, the user can’t select which emails get downloaded), I think the most useful reason for having Ethernet on a QL would be the sa...

Maybe a 6809 (Hitachi 6309) so that OS-9 or UniFlex can be run... Incidentally was/is OS-9/68K available for the QL? And what about the other way round with a more modern fast processor (maybe in FPGA) being used as the main processor with the QL being used as the I/O processor... Maybe even a super...