The Sinclair QL Forum

There are around 20 unbuilt Auroras left, so some could be made available. In principle more could be made, the CPLDs are still available, and for that matter the logic could be re-targeted. Aurora 8-bit makes a lot of sense on a Q68, good compromise between resolution and memory size. BTW I'd reall...

BTW how big is SMSQ/E for SGC with Aurora these days? I bet it would fit half a meg of flash and with plenty left for an alternative OS and extensions....

Even at 20MHz with an 8-bit bus it should work around GC speed, if a decent memory controller is implemented. At first sight this looks wrong to me. I have not actually measured timing on the GC, but it has 80 ns RAS access time DRAM chips, so I would guess DRAM cycle time around 150 ns, without us...

I really don't see things becoming much easier when using an 8-bit bus only. Only slower ;) The 68SEC000 20MHz version can BTW easily be overclocked to 50MHz - That would be close to achieving the 68020's speed, with a CPU that is much easier to obtain. Tobias Well, that has been counted on :P Even...

I wish I knew too.
But we know of other strange anomalies, like a certain basic compiler storing information into the top 3 bits of 32-bit addresses, so it will not work on systems with more than 256M of address space. Fortunately there are not many of those

Again, I understand, though in there you need to decode the SDHC and the boot ROM and a means to write protect the first 64k (don't forget this, GC and SGC both had problems with this) I also had strict write-protection for Qx0, but on the Q68 I tried with and without - never made a difference unde...

Is there an art to changing the clock speed of a running CPU? As the address decoder already knows when we're accessing the 8-bit space, dropping the clock from [FAST] to [STOCK] needs to be instant. My 68EC020FG25 runs happily at almost twice the listed 25 MHz. Don't even try, this is quite a nigh...

I was always under the impression that the whole copying ROM across, patching and paging and shadowing was only done for copyright reasons and could be made much simpler today when a 32-bit ROM could be temporarily paged in at $0 during the first and/or all RESETs and actually live way up in the ad...

I know, but you have to implement 90% of it or more, anyway. [...] The only difference is putting pull-up/down resistors on the bus in order to generate an initial PC I don't think so. I was also refering to ease of understanding, not just chip count. There is only one single, fixed, continuous $10...

This is basically how the SGC works, but it manipulates the decoder. [Explanation of SGC snipped] Ahem... the whole point of my idea was not to implement decoding, mapping and bus sizing as complicated as the SGC. ;) I know, but you have to implement 90% of it or more, anyway. I.e. once it gets int...