Search found 443 matches

by Nasta
Wed Sep 06, 2023 4:56 pm
Forum: Hardware
Topic: FPGA replacment for the ZX8301 ULA and more
Replies: 211
Views: 97446

Re: FPGA replacment for the ZX8301 ULA and more

The other approach is to control the clock going to the CPU - you can use a flip/flop or two within the FPGA to gate the clock signal to the CPU such that you get a 'glitchless' clock change - then you can select between a fast and slow clock. Any access to the ZX8302 can slow the CPU clock down if...
by Nasta
Wed Sep 06, 2023 11:51 am
Forum: Hardware
Topic: Ql Clone build
Replies: 21
Views: 7543

Re: Ql Clone build

tofro wrote: Tue Sep 05, 2023 9:15 pm
Peter wrote: Tue Sep 05, 2023 2:07 pm so I didn't want to bother the whole forum at this point.
Don't worry.
They'll be fine. :)
And very interested :)
by Nasta
Wed Sep 06, 2023 11:50 am
Forum: Hardware
Topic: FPGA replacment for the ZX8301 ULA and more
Replies: 211
Views: 97446

Re: FPGA replacment for the ZX8301 ULA and more

I think I solved it. I just delay 1 cycle bringing the DTACK low when PCENL is low and it now seems to work ok with 10Mhz cpu/ZX8301 clock and 7.5 Mhz ZX8302 clock. Just made the access cycle longer when talking to zx8302. This is the way to do it, and the way GC and SGC do it since their CPUs work...
by Nasta
Thu Aug 31, 2023 3:53 pm
Forum: Hardware
Topic: FPGA replacment for the ZX8301 ULA and more
Replies: 211
Views: 97446

Re: FPGA replacment for the ZX8301 ULA and more

If I am not mistaken the FPGA operates at 3.3V and I notice what seem like buffer chips to convert to 5V QL bus signals? If so, it might be a good idea to use a 68SEC000 chip on the 3.3V side coupled directly with the CPU and then convert signals that need to go to the QL bus to 5V. The chip has a s...
by Nasta
Mon Apr 17, 2023 6:43 pm
Forum: Hardware
Topic: "what-if" QL extended graphics
Replies: 45
Views: 11224

Re: "what-if" QL extended graphics

That being said you must not completely stop toggling RAS because it is used for the internal charge pump to negatively bias the substrate of the DRAM chips, without which the DRAM might consume too much current and not work right (a quirk of those older DRAM chips). Yes I forgot we discussed this ...
by Nasta
Mon Apr 10, 2023 11:53 pm
Forum: Hardware
Topic: "what-if" QL extended graphics
Replies: 45
Views: 11224

Re: "what-if" QL extended graphics

And with RASL/CASL of the QL's DRAM inactive, the multiplexer could be switched faster. I might overlook something, but I think even zero waitstates is doable despite the multiplexers. Fortunately the mux select and output enable lines are separate from RAS and CAS, as well as the DRAM WE. That bei...
by Nasta
Mon Apr 10, 2023 11:42 pm
Forum: Hardware
Topic: "what-if" QL extended graphics
Replies: 45
Views: 11224

Re: "what-if" QL extended graphics

And it is a bit more complicated, don't forget that ula in this bus has to check for the dsmc suddenly going high again by an expansion card and abort it's operation. So it can not function arbitrary fast or it will not give the card access. If it controlled all the ram and not the 128K it could ig...
by Nasta
Thu Jan 26, 2023 2:38 pm
Forum: Hardware
Topic: "what-if" QL extended graphics
Replies: 45
Views: 11224

Re: "what-if" QL extended graphics

Here's a little hint that might be useful: The QL memory map has an informal unassigned area of 16k right 'under' the bottom of the screen 0 RAM. Originally the on-board IO for the QL has been documented as residing in a 64k block of addresses starting at $10000, however, if one looks at what addres...
by Nasta
Wed Jan 11, 2023 11:17 am
Forum: Hardware
Topic: Gold Card byte-wide read access
Replies: 5
Views: 905

Re: Gold Card byte-wide read access

Unfortunately I don't have a GC, but I do remember there were several revisions of the INGOT for the GC, maybe that's the reason?