From what I can gather, Peter is limited to a 60MHz dot clock, which translates roughly into a 1024x768 pixel frame at 50Hz - this is the same on Aurora. That all being said, is it possible to center the 512 visible lines within the 768 line frame on the Q60? Some monitors are really finicky and wil...

I believe this is due to the limited speed the QL can communicate with the IPC, which ever that may be. As far as I understand it, it's a bit-bang affair, so the speed of the CPU and ultimately the (slow) speed of the QL bus will be the limiting factor, even over the rate the interrupt can be served...

IF SMSQ/E does not have to relocate it's code, there is no need to re-write the exception vectors. If it has to re-locate, then the need to rewrite the vectors is obvious as they have to track the relocation of the code. As far as I can tell, a static version is possible, but it needs more than acce...

The logic of he thing is easy - since there is (originally) a 68008 on the bus, this is what the hardware has to emulate. That being said, the 68k CPU does not offer much of help with this, even using a cycle re-run strategy requires a state machine that operates on a access cycle basis rather than ...

The biggest problem here is you are imagining a whole lot of 'magic' where there is none. Have a look at what the 68008 does when accessing a word or long word - it simply does a series of byte accesses. A 68000 does the same with word accesses (since it's bus is word-wide) when doing a long word ac...

It almost seems to make more sense to replicate the operation of the Aurora but in an FPGA that could be offered as a plug in replacement or plug in card ? You could design it from the get go for VGA / DVI / HDMI output. Exactly, and that is how Miracle's original Masterpiece graphics card started ...

I have also wondered how 68008 does read and write 16, and 32 byte entities over 8-bit data bus. No big mystery there - it's all explained in the 68000/8 user manual, it basically breaks larger transfers into a series of byte transfers, at least 4 clock cycles per transfer. That being said, because...

with VSYNCH occuring at approximately line 288, if someone needs a precise number I'll re-measure this. Do you know at what point IPL1 is triggered? At the same time as VSYNCH? Not sure as this is done by the 8302 (it has a VSYNCH input for this), but I would assume at the rising edge of VSYNCH plu...

What could have been improved? Well, aside from the issue of using a 16MHz clock rather than 7.5HMz (which also has repercussions on the 8302 as the CPU clock is used for baud rate generation), the biggest improvement to be gained would have been handling the invisible vertical retrace period in a m...

The curse of issue 5 As stated before, the main difference between issue 5 and issue 6 boards is the HAL chip. However, on inspection, it does quite a bit more than just replacing a single 74LS03 chip. In fact, it also connects the 8302 directly to the CPU bus and decodes it instead of the 8301, lea...