Close, but no cigar..

[Derek_Stewart]

Hi Peter,

No Gerber files exist.

Also it was an exercise in getting to know how to you PCB design software

[Pr0f]

Might be an interesting exercise to produce a new 16 bit design of the aurora with 16 bit wide data path's and a 16 bit x 256K Dual ported VRAM - some of these RAM chips are quite sophisticated and offer settable start and end points for the serial access port - which is 16 bit's wide as well - giving you the "full" set of RGB values in a single cycle. The original MAC / PEM combination pulled off some clever techniques to get all those video modes in the design, but I've found a lot of that is actually provided in the VRAM chip natively.

Aside from the basic video timing, you need to decide what to do with the 16 bits of video data - which would depend on the video mode.

As a side project I am looking at the viability of adding that to a 16 bit wide QL design.

[Pr0f]

Might be an interesting exercise to produce a new 16 bit design of the aurora with 16 bit wide data path's and a 16 bit x 256K Dual ported VRAM - some of these RAM chips are quite sophisticated and offer settable start and end points for the serial access port - which is 16 bit's wide as well - giving you the "full" set of RGB values in a single cycle. The original MAC / PEM combination pulled off some clever techniques to get all those video modes in the design, but I've found a lot of that is actually provided in the VRAM chip natively.

The VRAM I was looking at - TMS55160-60DGH, it has a bigger brother with double the Serial access port size, but 256x16 covers a lot of pixels in a good number of colours (that's 512 pixels across at 8 bits per pixel)

Aside from the basic video timing, you need to decide what to do with the 16 bits of video data - which would depend on the video mode.

As a side project I am looking at the viability of adding that to a 16 bit wide QL design.

[Pr0f]

Well - the SGC works fine in an Issue 7 QL. Interestingly it was the first time I used this combination:

QL power converter
QL PICO VGA

I need to retrofit a regulator to the Qubide board so that I can test this in the same QL. So that's one for tomorrow...

[Pr0f]

I am adding a couple of pictures showing the boot up screens with the SGC and the modified QUBIDE

There was an error in the QUBIDE - on the little piggy back board carrying the other GAL - A4 and A5 were shorted, so the QUBIDE produced the boot banner and then just filled the screen with garbage - the picture attached shows the interface now corrected.

I still need to tackle the ROM not recognized, which must be an issue on the Aurora board. Today has been mostly testing the address lines to the MACH chip and ROM socket on Aurora - which are all ok with the exception that A15 is via a 470R resistor - and I am wondering if this is not driving the Flash chip properly. It's one area where I might consider reducing this to 300R

Also plan on removing cleaning and reseating all 3 of the PLCC Logic chips, and re-sweating the solder joints as there was a lot of varnish like material just on these pins on the underside of the board. I will test the board before mounting it back in the pandora housing - as it's a pig to get to once it's in there!

Oh - that red jumper on the Qubide board selects between Rebel 2.01 firmware and the QUBATA firmware

[Pr0f]

OK - so the issue does appear to be with the Aurora, pared everything back to it's most basic - so just the SGC and Aurora and I still get the ROM Message.

I did a bit of work on the Aurora board:

Removed the main logic chips one by one, used some contact cleaner and deoxidizer on the sockets, gave them a clean - there was some dirt there. I resoldered the sockets to, just in case of any dry joints.

Also - after reviewing the circuit diagram - I removed the diode and 470R resistor that provide A15 or RA0 to pin 3 of the ROM socket - the 470 ohm is now replaced with a wire link - this mean that you can now only jumper this pin for VCC or for A15.

I checked continuity for the address lines from the 64 pin Euro connector to the ROM chip and to the MAC logic chip - these are all good.

After all that work, I plugged the minimal setup back together and was greeted by the Minerva logo - but the rest was just a black screen and nothing else...

A subsequent reset produced the ROM error message again, and then the interface now just delivers a red screen with dots in the video.

I powered off, and removed the SGC card - powered back on and I get the same red screen with dots - so this is what you would expect with no processor attached.

So basically it looks like I need a new Aurora board - or if anyone has a bare PCB - I don't mind building one up from the ground up. I suspect there was more than one burned trace on this board (I could not find a trace from the diode that went to RA0 on the QAG logic chip - so unless that's a buried trace in the inner layers, that's also gone.

[Derek_Stewart]

Hi,

I have nearly a Aurora PCB file in KiCad.

The Aurora PCB was drawn up on and old Tango CAD program (which has later evolved into Protel and then Altium) did not have a flood fill function. The PCB file was in Altium Designer 22, but I moved it to KiCad 7, which allows me to use Linux rather than Windows.

I generated new Ground and Power Planes on the inner PCB layers and I am in the process of verifying the PCB Tracks by manual routing of the tracks to the Schematic GIF file.

There does seem some slight difference from the Schematic and the PCB, mainly Track Net names and omissions of resistor names, which I am redrawing a the Schematic.

The main problem was programming the MACH chips, and whether new MACH 2xx/3xx PLDs can be purchased. Porting the HDL code to a new chipset, may require manual coding all the HDL code. which seems to pre-date Verilog and VDHL, In MACHXL Description Language. Maybe Leon's 8301 FPGA replacement is a good approach, it work with QIMSI and all other QL expansions.

But I will continue with the PCB/Schematic update, as it is a good way of learning how to use PCB CAD packages. It seems that Kicad is food at generating PCB files from Gerber files and has the same NET name editing as Altium Designer.

Just wish I had something like this on the QL, maybe I have time to write the software, since I have no soldering to do now...

[Pr0f]

Hi Anyone - if you have an Aurora board to hand - are you able to post a detailed closeup picture of the top and bottom of the PCB in the area of the QAG (this is the smaller CPLD chip near the OS ROM socket on Aurora - ideally including the ROM socket (with chip is fine) and the bottom of the larger CPLD chip (the MAC) and the whole of the QAG chip.

[tetroid]

Hi Anyone - if you have an Aurora board to hand - are you able to post a detailed closeup picture of the top and bottom of the PCB in the area of the QAG (this is the smaller CPLD chip near the OS ROM socket on Aurora - ideally including the ROM socket (with chip is fine) and the bottom of the larger CPLD chip (the MAC) and the whole of the QAG chip.

[Pr0f]

So that does answer my question - there are tracks in the middle layers!

Thanks for posting the picture

I spent an evening 'bussing' out the data, control and address lines between the edge connector and the MAC, QAG and ROM socket - all seem to be in order. I also checked that VCC and Ground connections were all good on the MAC and QAG - I am taking the view that as I am getting good video output - the issue is less likely to be with the PE chip, and in any case that does not interfere with data or address lines on the edge connector - interfacing only with the other logic chips and the SAM side of the VRAM.

It's an odd problem for sure.