Hi,
I'm making some good progress in the design and the main board. For the CPU/RAM board, the main job that remains is to swap the 8301 with lliont's altera CPLD replacement. For the 8302, thanks for all the suggestions. I'm still focused on keeping the original ROMs and avoiding the need to re-write the IPCOM or keyboard handler if at all possible. This will likely mean implementing some basic 8302 functions in a CPLD and using either an 8749, or as suggested, an ATMEGA for the PS2 kb interface.
I've dug a little deeper into the IPCOM handler and 8049 code. The bit banged interface seems fairly straightforward - probably pretty similar to the COMMSDATA/CLK one used in the Sinclair interface 1 ULA. Writing x18003 D3 looks like it provides data out (to the 8049) and reading x18020 D7 is data in (from 8049, with D6 handshake). Interpreting the nibbles/bytes for the IPCOM 8 and 9 keyboard commands could be done by the arduino and then shifting out the relevant PS2 keyboard codes/status nibbles/bytes. Before I start on this in earnest, has something similar been implemented before ?
The other bit that is causing me a little confusion is the 8302 interrupt control system. Is it just passing vysnc to IPL1 ? Or will I need to implement the latches/reset for vsync, external (and IPC/Serial) interrupts on x18021 ?
Apologies for all the questions - I'm just trying the understand how the hardware works!
Ql Clone build
Re: Ql Clone build
@Peter - thanks for your msg. Apologies I can't reply directly because, as a newbie, I can't send messages for a bit. I am very interested in the schematic you mentioned as it may give me some ideas for my first iteration - and will be much more flexible for developing hardware for the second. I'm hoping I should be able to msg you after a few more posts here.
Re: Ql Clone build
Hi Andy,
thanks and I wasn't aware that you can not reply to a PM. A Qzero based approach would be fundamentally different from a 68008 based approach, so I didn't want to bother the whole forum at this point. Still it could be a nice tinkering project - and much higher spec perfomance-wise.
All the best, Peter
thanks and I wasn't aware that you can not reply to a PM. A Qzero based approach would be fundamentally different from a 68008 based approach, so I didn't want to bother the whole forum at this point. Still it could be a nice tinkering project - and much higher spec perfomance-wise.
All the best, Peter
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vanpeebles
- Commissario Pebbli
- Posts: 2821
- Joined: Sat Nov 20, 2010 7:13 pm
- Location: North East UK
Re: Ql Clone build
Hi Andy,
so here were go. QLbase is a little QL Mainboard replacement, mainly meant as an example for other board designs in different form factors etc.
I plan to publish the schematics at some point. At the moment I only provide them privately to friendly tinkerers, to limit the amount of Q&A.
It is a direct fit to the QL case, no case modding. Instead of a 60008+ULAs, it uses a Qzero as compute module. Operating systems Minerva and SMSQ/E.
QLbase has an 8 bit ATmega328P (Arduino compatible) as IPC instead of the QL's 8049. The video output is highcolor LVDS (not to say HDMI). VGA with only 8 colors optional. Supports the QL Matrix keyboard with a direct connection, QL Network at the original QL locations, the QL Speaker, the QL LEDs. The QL Reset button is re-used as power switch. QL Joystick 1 and SER 1 over D-Sub 9 pin connector with ribbon cable. PS2/2 mouse & keyboard as well as buffered realtime clock are also supported.
The connectors named "Qzero video" and "Qzero I/O" are used to plug in a Qzero module. I'm happy if you look at the QLbase schematics and derive your own QL clone from it. But likely that would be something completely different than what you had in mind.
All the best
Peter
so here were go. QLbase is a little QL Mainboard replacement, mainly meant as an example for other board designs in different form factors etc.
I plan to publish the schematics at some point. At the moment I only provide them privately to friendly tinkerers, to limit the amount of Q&A.
It is a direct fit to the QL case, no case modding. Instead of a 60008+ULAs, it uses a Qzero as compute module. Operating systems Minerva and SMSQ/E.
QLbase has an 8 bit ATmega328P (Arduino compatible) as IPC instead of the QL's 8049. The video output is highcolor LVDS (not to say HDMI). VGA with only 8 colors optional. Supports the QL Matrix keyboard with a direct connection, QL Network at the original QL locations, the QL Speaker, the QL LEDs. The QL Reset button is re-used as power switch. QL Joystick 1 and SER 1 over D-Sub 9 pin connector with ribbon cable. PS2/2 mouse & keyboard as well as buffered realtime clock are also supported.
All the best
Peter
Re: Ql Clone build
Hi,
Got the first PCB back for my QL board and populated it. It uses either Lliont's CPLD replacement or the original ZX8301, and 4464s for RAM. A picture of the first version of the board is attached below - and you can see the handful of RAM routing errors (doh!) fixed with jumper wires. CPU, ROM, RAM and display appears to be working. I've not implemented the IO system yet (ZX8302 and IPC clone).
At the moment it initialises to a white screen (JS ROM) or minerva logo (minerva 1.98 ROM). I expect the std ROMs are waiting for the (missing) I/O system to respond before getting to the copyright message/prompt.
The QL service manual seems to indicate the ZX8302 (and possibly the IPC) need to to be working for the system to fully boot. This would provide the std I/O ports, IPC Comms and interrupts missing from my first PCB.
Can anyone give me a steer on the minimum hardware needed for the QL to fully boot (it doesn't have to be useable - yet) ? Or if there is a forgiving test QL ROM available ? I've taken a look at the Minerva source but I'm having trouble understanding the assembler (Z80 is more my thing) so cannot make out what is needed.
Many thanks,
Andy.
Got the first PCB back for my QL board and populated it. It uses either Lliont's CPLD replacement or the original ZX8301, and 4464s for RAM. A picture of the first version of the board is attached below - and you can see the handful of RAM routing errors (doh!) fixed with jumper wires. CPU, ROM, RAM and display appears to be working. I've not implemented the IO system yet (ZX8302 and IPC clone).
At the moment it initialises to a white screen (JS ROM) or minerva logo (minerva 1.98 ROM). I expect the std ROMs are waiting for the (missing) I/O system to respond before getting to the copyright message/prompt.
The QL service manual seems to indicate the ZX8302 (and possibly the IPC) need to to be working for the system to fully boot. This would provide the std I/O ports, IPC Comms and interrupts missing from my first PCB.
Can anyone give me a steer on the minimum hardware needed for the QL to fully boot (it doesn't have to be useable - yet) ? Or if there is a forgiving test QL ROM available ? I've taken a look at the Minerva source but I'm having trouble understanding the assembler (Z80 is more my thing) so cannot make out what is needed.
Many thanks,
Andy.
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Derek_Stewart
- Font of All Knowledge
- Posts: 3975
- Joined: Mon Dec 20, 2010 11:40 am
- Location: Sunny Runcorn, Cheshire, UK
Re: Ql Clone build
Hi,
The Minerva ram test on power up is quite an aggressive ram test, I was told by the designers once that Minerva test the QL ram and return the best possible ram available, 64K was a lowest value, but whether this works in
practise is another question. Using the RAMFAIL program will give the location of the Internal RAM fault. Whereas with JS or JM etc... ram failures are white screen and the process detailed in the Service Manual by raising the ram data lines high is a way to find the ram fault, maybe not a good way.
Usually when the large red Minerva logo is only displayed on the screen, this usually means failure of the 8049.
The Minerva ram test on power up is quite an aggressive ram test, I was told by the designers once that Minerva test the QL ram and return the best possible ram available, 64K was a lowest value, but whether this works in
practise is another question. Using the RAMFAIL program will give the location of the Internal RAM fault. Whereas with JS or JM etc... ram failures are white screen and the process detailed in the Service Manual by raising the ram data lines high is a way to find the ram fault, maybe not a good way.
Usually when the large red Minerva logo is only displayed on the screen, this usually means failure of the 8049.
Regards,
Derek
Derek
Re: Ql Clone build
Hi Derek,
Thanks for the detail. Since my last post, I found one of the RAM chips on my design was (eventually) slightly warm and drawing more current than the others. My chips are from Ali so may not have been the best. Now this has been replaced, the system boots up using the JSROM to the copyright/monitor select menu. It's all very encouraging!
The steer on the Minerva ROM is useful. I've deliberately introduced some RAM faults by provided a poor +5V supply to one chip and the ROM displays a three line error code using colour blocks. Once the chip has a solid supply it consistently boots to the red logo in the bottom right of the screen. Having the logo only must (hopefully?) be due to the 8049 failure. I've not implemented this and the 8302 ULA yet.
Cheers,
Andy.
Thanks for the detail. Since my last post, I found one of the RAM chips on my design was (eventually) slightly warm and drawing more current than the others. My chips are from Ali so may not have been the best. Now this has been replaced, the system boots up using the JSROM to the copyright/monitor select menu. It's all very encouraging!
The steer on the Minerva ROM is useful. I've deliberately introduced some RAM faults by provided a poor +5V supply to one chip and the ROM displays a three line error code using colour blocks. Once the chip has a solid supply it consistently boots to the red logo in the bottom right of the screen. Having the logo only must (hopefully?) be due to the 8049 failure. I've not implemented this and the 8302 ULA yet.
Cheers,
Andy.