Since the thing is SRAM based, memory expansion requires the full address and data line set. This is not going to be on the expansion connector, nor should it, the signal speeds there are far too critical and fast, This remains local to the CPU and is not seen on outside buses. If it is expandable, there is a piggyback board with it's own connectors.
Expansion buses MUST be buffered, not only for signal strength but integrity and RFI. Signals toggle on the external bus only when it is accessed.
With regards to those, we still need some simpler way of expansion using an 8-bit bus and a means to use (at least in the beginning) existing QL peripherals. So a suitable subset of the J1 signals should be provided anyway. Regarding address and data lines, you can't save anything as 16k + bank select for all 16k slots = full address lines. Based on the QL's architecture and existing peripherals, one could at best save one address line (in theory, A18..19 being 01 and 10 are not used as this would address an old QL RAM 512k RAM expansion, rather superfluous with existing 32-bit RAM of at least 8x the size).
On the other hand, there are peripherals that would benefit from a wide bus, and in fact some that really only make sense with a wide bus, the lattger notably being extended graphics. That being said, you do not need (nor do you have) the full addressing capability of the CPU, but you could manage up to 2M, because that's what's left in the address map assuming one day all QL style peripherals are phased out. And THAT being said, looking at the way the WMAN/PTRGEN work, even 1M of screen memory is pushing it, given 12M of RAM.
A simple protocol is possible that adds 24 more bits and 2 data transfer acknowledge lines to the third row of the connector, that would offer approximately 8-10x QL bus transfer speed, still remaining conservative on signal speeds - most of the transfer rate improvement comes from the 4x wider bus. This is not that important for file devices as QL files are miniscule by today's standards, but for any usable graphics it's an absolute necessity.
So, to summarise:
If you think of this board as a standard card with a connector on each end, you end up with a standard 2-row expansion connector on the right side - this plugs into an existing 'QL motherboard', even one 'cut down' with 2 DRAM chips, 8301, 8302, IPC and a few MSI chips to emulate the old QL. You could just as well put that into the original case. One could also use an Aurora here - still fit the whole thing inside the old case. In the future, this 'right hand expansion' would hold the basics, like keyboard, RTC, mouse, some basic storage device, some sort of serial and parallel port. In any case the basics of a 'motherboard', which are usually not extremely fast devices but are then easily connected through an 8-bit bus (which BTW may also get a new 'fast' mode).
The full connector, with an extra row, would be on the left side, where a regular through connector would be. In the beginning, one could sue regular QL peripherals here, just like before. One could also connect a QL style, or even better, and expanded backplane with 3-row connectors. Or - a card that combines new video and a faster mass storage device, perhaps hot plug/swap capable, like an SD card or a SATA port. So, that when 3 boards would be combined, it could STILL fit inside the old case
and if you want something more compact, you can use a backplane of some sort.
It should be noted that the CPU automatic bus sizing mechanism enables this approach to work just like the old QL bus - any part of the 2M address map dedicated to expansion can hold a 32-bit peripheral because the CPU expects the peripheral to tell it how wide it is when it ends the access (at which point the CPU sets itself up to execute additional accesses if the bus was narrower than 32 bits which it assumes at the start). Thus a 32-bit peripheral can be made that over-rides or shadows an existing 8-bit one, using all the same lines for all the same purpose as before, if one wanted it.