FPGA replacment for the ZX8301 ULA and more

[lliont]

I believe those cards can take over the QL as it is, I don't need to do anything special for it. Because the fpga releases all the resources, all the 2 MB ram with the same mechanism (DSMC high) as the standard did for the low ram.

[janbredenbeek]

This will require to disconnect one of the A18 or A19 pins of the expansion and replace it with A21, clever trick and may work if Minerva tries to look for drivers up there. It is true that both Minerva and QDOS look for ram as long as they find more but does Minerva look for driver rom beyond 1MB? up to where?
And if it does then Minerva will detect the same driver many times as there will be mirror images (maybe I can take care of this).

Minerva's ROM scan is quite sophisticated. It scans at $C000,$10000,$14000 and then from top of RAM upwards until it discovers a wrap to it's own ROM address (the $4C024C02 long word at address zero). Also, duplicate extension ROMs (due to incomplete decoding) are discovered (by comparing the first 512 bytes to any lower ROM image found) and skipped.

[lliont]

This is very nice thanks for the info

[Derek_Stewart]

Hi,

This looks a really excellent expansion for the QL, I like the addition of Sprites, this shoukd allow good looking games to be written.

Can the Minerva Second Screen be usdd with the extra ram, or is there a better way to implement access to the extra ram.

[Nasta]

If I am not mistaken the FPGA operates at 3.3V and I notice what seem like buffer chips to convert to 5V QL bus signals?
If so, it might be a good idea to use a 68SEC000 chip on the 3.3V side coupled directly with the CPU and then convert signals that need to go to the QL bus to 5V.
The chip has a statically selectable bus width so can operate like a 68008 but with a 16M address space and full 7 levels of interrupt, though that would not be easily usable in the QL. It would actually be possible to add address lines to the external bus using signals which exist on the 68008 CPU but were never used, like the FC lines and E (the latter was used on the QEP EPROM programmer but that incompatibility is a small price to pay for extra capability). The much lower power consumption is a nice bonus.
One more thing - driving output only lines, eg. address and control lines with 3.3V levels is OK if it's only the on-board CPU driving them. Things get more complex if there is a Gold or Super Gold Card in the picture because it disables the on-board CPU's signals and drives it's own. What is important is that these accelerators drive at 5V levels and while the on-board CPU is disabled, it's pins are still connected to the bus and if it used 3.3V levels and is not 5V tolerant, there will be problems.

[lliont]

Hi,

This looks a really excellent expansion for the QL, I like the addition of Sprites, this shoukd allow good looking games to be written.

Can the Minerva Second Screen be usdd with the extra ram, or is there a better way to implement access to the extra ram.

Hi,
extra video ram is inside the fpga and mapped high at the 2 MB ram and finally I will probably map it high at the 4MB end.
For now the Second screen Minerva screen works as before but without the extra colors.

[lliont]

One more thing - driving output only lines, eg. address and control lines with 3.3V levels is OK if it's only the on-board CPU driving them. Things get more complex if there is a Gold or Super Gold Card in the picture because it disables the on-board CPU's signals and drives it's own. What is important is that these accelerators drive at 5V levels and while the on-board CPU is disabled, it's pins are still connected to the bus and if it used 3.3V levels and is not 5V tolerant, there will be problems.

Just for info, I buffer and level convert all the lines, input and output. There are 2 more buffer chips under the pcb.
And there are two pcb's one for the cpu and the other for the fpga-ram they are independent and the fpga board via cables connect to get A18 to A21 signals + the reset signal and optionally provide a, separate from the ql system, clock to the cpu (I don't use this at the moment and don't know if it can work, I mean run the cpu and zx8301 in higher speed than the zx8302).

[lliont]

I see that MC68SEC000 works both at 3.3V and 5V and goes up to 20Mhz, so it could be a nice replacement.

[lliont]

I run the system for a short period at 10Mhz and although the video was distorted and video timing needed corrections it booted ok.
But I don't know if zx8302 will have problem constantly running at 10Mhz.

Now I'll run for a while at 8Mhz the cpu and ZX8302 and run ZX8301 at 16Mhz and the video at 10.666667 Mhz so I don't have to change the video to work.

[Pr0f]

I think the ZX8302 itself can run faster - as people have tried it - the issue is it provides critical timing based on the CPU clock for the baud rate for serial transmission (and if not using Hermes IPC) for the IPC on the BAUDX4 output. Also NET and Microdrive timing affected. I suspect it would happily sit on a CPU bus running a faster CPU clock though, and still have the Clock input at 7.5MHz.