Fun things to do with an MC68EC020....

Nagging hardware related question? Post here!
User avatar
Dave
SandySuperQDave
Posts: 2765
Joined: Sat Jan 22, 2011 6:52 am
Location: Austin, TX
Contact:

Re: Fun things to do with an MC68EC020....

Post by Dave »

I can breathe!

The air here is clean and fresh. It is very stimulating. Lots of ideas. Getting here was tiring though.


User avatar
Dave
SandySuperQDave
Posts: 2765
Joined: Sat Jan 22, 2011 6:52 am
Location: Austin, TX
Contact:

Re: Fun things to do with an MC68EC020....

Post by Dave »

Aaaand I'm back! It was nice to see the mountains even if I couldn't climb all over them.

Soooo, back to wor<<<hobbying!


User avatar
Dave
SandySuperQDave
Posts: 2765
Joined: Sat Jan 22, 2011 6:52 am
Location: Austin, TX
Contact:

Re: Fun things to do with an MC68EC020....

Post by Dave »

The Bill of Materials is starting to take shape:

MC68EC020FG25 (x1 $3.50)
CY62167E 16Mb 1M x 16 SRAM (x6 for 12MB, $60) OR (x2 for 4MB, $20)
29F040 (x2 $2.00)
CPLD (TBD ~$5.00)

Assorted power, buffer, caps, connectors available or on hand.

Will start ordering parts I don't already have this week :)


User avatar
Peter
QL Wafer Drive
Posts: 1953
Joined: Sat Jan 22, 2011 8:47 am

Re: Fun things to do with an MC68EC020....

Post by Peter »

If you wish to add a realtime clock with integrated crystal and charger, you could take the DS1374C also used on the Q68.


User avatar
Dave
SandySuperQDave
Posts: 2765
Joined: Sat Jan 22, 2011 6:52 am
Location: Austin, TX
Contact:

Re: Fun things to do with an MC68EC020....

Post by Dave »

Neat chip! That's really helpful. :D

If we implement it the exact same way you have, it would make supporting it in SMSQ/E a lot easier.


User avatar
Peter
QL Wafer Drive
Posts: 1953
Joined: Sat Jan 22, 2011 8:47 am

Re: Fun things to do with an MC68EC020....

Post by Peter »

The Q68 uses bitbanging for the RTC, as it's only read at startup and not speed critical. One unidirectional output register for the I2C clock. And one "open drain" input/output for I2C data. Should be easy to implement. I wrote a little C Program to set the clock, which should also work for you, after adjusting addresses. The nice thing about the DS1374C is that it can hold the seconds exactly in QL PC.CLOCK format.

I use a "gold cap" with the DS1374C so there is no battery that could suffer over the years.

I checked the Q68 serial port, if that could be useful for your project also, but it uses too many registers for a CPLD.


User avatar
Dave
SandySuperQDave
Posts: 2765
Joined: Sat Jan 22, 2011 6:52 am
Location: Austin, TX
Contact:

Re: Fun things to do with an MC68EC020....

Post by Dave »

I ordered 100 CPUs today.


User avatar
Dave
SandySuperQDave
Posts: 2765
Joined: Sat Jan 22, 2011 6:52 am
Location: Austin, TX
Contact:

Re: Fun things to do with an MC68EC020....

Post by Dave »

I'm choosing memory devices this weekend. I have selected the product range - just now picking the specific device.

I found a nice range of Cypress SRAMs designed for mobile and automotive use. They're organized as 16Mb, 1M x 16. So, two ICs give 4MB of 32-bit RAM for around $20. This gives us 2x1 = 4MB, 2x2 = 8MB and 2x3 = 12MB.

It's available in a range of voltages; 1.8, 3.3 and 5V so obviously 5V selects itself.

It's available as ECC and non-ECC, so non-ECC obviously selects itself. Unless someone can think of a fun thing to do with the extra bit.

It's available in 45ns and 55ns versions. I'm curious if anyone has any thoughts on these. 55ns is a natural frequency of 18MHz, and 45ns is a natural frequency of 22.5 MHz. Now, I realise it takes four clock cycles to do anything on the 68020, but the higher devices can take significantly less due to pipelining and cache improvements.

Is there any advantage to buying the 45ns part, or can it cause problems?

What speed part would I need to look at if I later tried to apply this design to a much faster CPU target, like the 68060/60?

Does SRAM hold its outputs indefinitely until the next event happens, or does it fade and become unstable like DRAM? (Not that this is an issue, but I'd like to know as I am also looking at a 68SEC000 CPU that is fully static and can be clocked down to 0.)


User avatar
Dave
SandySuperQDave
Posts: 2765
Joined: Sat Jan 22, 2011 6:52 am
Location: Austin, TX
Contact:

Re: Fun things to do with an MC68EC020....

Post by Dave »

Also, this product works as 1M x 16 or 2M x 8, so that give the option of stacking 8MB as 2x2 or 4x1. 4x1 reduces bus loading a little. 12MB could be stacked as 4x1 and 1x2 so there are 2 devices on each line instead of 3, but that could get fiddly. So, since these devices have such light bus loadings anyway it just makes sense to configure them as 16-bit, and organize them as 2x1 for 4MB, 2x2 for 8MB and 2x3 for 12MB. The expansion port would be fully buffered, so.... :D

Just explaining that it is an option, and that this RAM works as an 8-bit device also, which may be suited for other more traditional designs.

This SRAM is suited to TTL levels but not CMOS levels. I did a word search on the 68SEC000 which is a fully HCMOS device but I'm unclear if it would be compatible. I suspect it would be. That said, I've decided the 68SEC000 is uninteresting in the BBQL use case because it has the same cost as the 68EC020 but has a limited performance benefit.


User avatar
tofro
Font of All Knowledge
Posts: 2685
Joined: Sun Feb 13, 2011 10:53 pm
Location: SW Germany

Re: Fun things to do with an MC68EC020....

Post by tofro »

Dave wrote: It's available in 45ns and 55ns versions. I'm curious if anyone has any thoughts on these. 55ns is a natural frequency of 18MHz, and 45ns is a natural frequency of 22.5 MHz. Now, I realise it takes four clock cycles to do anything on the 68020, but the higher devices can take significantly less due to pipelining and cache improvements.

Is there any advantage to buying the 45ns part, or can it cause problems?
As the 68k memory interface is asynchronous, speed actually doesn't matter much - The CPU will accommodate. And higher speed is normally an advantage, but you are already way faster than what a 68040 could really use. Modern PC DRAM SIMMs for GHz CPUs typically are somewhere around that range (40-60ns).
Dave wrote:
Does SRAM hold its outputs indefinitely until the next event happens, or does it fade and become unstable like DRAM? (Not that this is an issue, but I'd like to know as I am also looking at a 68SEC000 CPU that is fully static and can be clocked down to 0.)
Yep, SRAM is designed to hold its contents with no further action as long as Vcc is applied. It consists of flip-flops rather than capacitive storage in DRAMs and doesn't need any refresh activity. If I guess right what you've selected, the Cypress SDRAM even has a sleep mode that powers down the RAM if address lines don't show activity.

Tobias


ʎɐqǝ ɯoɹɟ ǝq oʇ ƃuᴉoƃ ʇou sᴉ pɹɐoqʎǝʞ ʇxǝu ʎɯ 'ɹɐǝp ɥO
Post Reply