Re: Gold Card / Super Gold Card ROM patching...
Posted: Mon Dec 18, 2017 8:52 am
Im guessing there is no-one left with the financial clout to sue someone in RussiaPeter wrote: How about the recent GoldCard clones then?
RIP Sir Clive Sinclair 1940 - 2021
https://qlforum.co.uk/
Im guessing there is no-one left with the financial clout to sue someone in RussiaPeter wrote: How about the recent GoldCard clones then?
Serial transmission is handled by hardware in the 8302. I'm not sure about the driver getting replaced.Pr0f wrote:I thought I would share my findings - thanks to Jan to show what the Gold/Super Gold actually do to the Minerva code in terms of patching:
(list skipped...)
So that deals with the Microdrive and I2C timing critical code, so I am guessing that Serial transmission and Networking are handled through driver replacements?
Well I expect my Q68 to arrive before Christmas, I guess for me this will be some other holiday's projectPerhaps a Christmas holiday project to disassemble the Gold card ROM sections - certainly now I have some entry points to look into.
That's only for reception - serial transmission is done by the CPU and is bit banged, using a couple of bits in one of the zx8302 registers.janbredenbeek wrote:Serial transmission is handled by hardware in the 8302. I'm not sure about the driver getting replaced.?
The Gold/Super Gold cards take the L2 interrupt from the QL bus, and that is raised by the ZX8302 for various conditions (serial data available, Microdrive data, IPC communications, and frame interrupt), the timing of this is effectively independent of CPU speed, as apart from the frame interrupt, these are asynchronous events. The Aurora goes to some trouble to ensure the approx. 50hz original vsync timing appears on the same line, so as not to upset this timing. The ZX8302 has 2 registers for to capture bytes from the MDV, so some of the timing burden is taken away from the CPU, so it doesn't have to look for edges.janbredenbeek wrote:One interesting point would be the interrupt serving code in the ROM which handles MDV I/O, the GC ROM must patch this one way or another because of the different timings. From your list I gather the L2 interrupt vector hasn't been changed.
Whilst quite a bit of preparation seems to take place before QDOS writes to the 8302 for SERial transmission, the actual transfer is byte orientated (to the 8bit pc_tdata register), not bit-banged per-se.Pr0f wrote:janbredenbeek wrote:serial transmission is done by the CPU and is bit banged, using a couple of bits in one of the zx8302 registers.
Hermes or SuperHermes?Dave wrote:Which raises the point that there may be a world market for a half dozen more Hermes. Given the nominal economic potential, it might be a nice Christmas present if the source of Hermes were released with any notes so people could possibly develop or embed it further? Then it could find a new life? I would be happy to pay a FRAND license fee for it.
Maybe an alternate replacement for the IPC? The disassembly for the original 8049 is available, and there is good documentation for the message passing between ipc trap and the ipc.Dave wrote:Which raises the point that there may be a world market for a half dozen more Hermes. Given the nominal economic potential, it might be a nice Christmas present if the source of Hermes were released with any notes so people could possibly develop or embed it further? Then it could find a new life? I would be happy to pay a FRAND license fee for it.
All the more benefit to open it up once your existing stock is consumed. A lot of smart people in the community could possibly quickly provide extended serial capabilities, etc. which is one of the biggest advantages of updating the IPC.RWAP wrote:Hermes or SuperHermes?
I have some Hermes in stock but Tony Firshman has been unable to make any new SuperHermes as he could not get the keyboard code to work for some reason