Qubbide Extended drives

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Pr0f
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Qubbide Extended drives

Postby Pr0f » Fri Oct 13, 2017 1:07 pm

I've seen in the manual for Qubbide the mention of multiple Master drives upto 8 or 16 depending on where you read it. How is that done?

I have GAL equations for Qubbide - not sure which version, but these have the amendment for alternate status register - dated 1998 Jul 07.

Looking at the manual and the GAL logic - is it just a case of replicating the smaller GAL chip that carries the control signals for the 16 byte I/O area for each new Mater and additionally decoding out A7-A4 for each of Drive selectors - and leaving the original GAL logic intact to drive the latches ?

Basically replicating this equation with more address lines in the 2nd GAL:

/* GAL1 is selected in the last 256 bytes */
SEL = A13 & A12 & A11 & A10 & A9 & A8 & !ENL;

e.g.
SEL0 = A13 & A12 & A11 & A10 & A9 & A8 & !A7 & !A6 & !A5 & !A4 & !ENL;
SEL1 = A13 & A12 & A11 & A10 & A9 & A8 & !A7 & !A6 & !A5 & A4 & !ENL;
...

and so on, changing the logic selection levels for A7-A4 for each Master drive select ?


Nasta
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Re: Qubbide Extended drives

Postby Nasta » Thu Oct 19, 2017 11:23 pm

No, IDE bus signals CS1/CS3 or IOR/IOW are further decoded, generating up to 16 pairs of signals, one for each master/slave drive combination. Each pair of signals is decoded based on the state of address lines A4..A7, independent of anything else. The rest of the IDE signals are shared between all drives.
Also, less than 16 can be used - 2, 4, 8 are also possible, decoded by A4, A4..5, A4..6 respectively.
What signals are decoded depends on the way the cable(s) connect. If everything is connected to the same cable (with some extra lines to implement decoding), i.e. one ribbon cable with multiple connectors, CS1/CS3 are decoded. If multiple connectors are used to run a cable to each master-slave pair, then it's better to decode IOR/IOW and route one pair onto each connector.


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Pr0f
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Re: Qubbide Extended drives

Postby Pr0f » Fri Oct 20, 2017 11:17 am

Ah, thanks :D

That makes sense. So we are making the CS lines more granular, but still using the overall select for that I/O area to gate the other signals through the GAL(s)

I was planning on decoding 4, so just need to use 2 of the address lines A4 and A5 then.

Many thanks for the response.


Nasta
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Re: Qubbide Extended drives

Postby Nasta » Fri Oct 20, 2017 4:12 pm

Yes exactly. In the case of the original QUBIDE, if I remember correctly, IOR/IOW is gated by DSL. Adding a decoder may produce too much of a delay.
CS1/CS3 are only generated from address lines, so this is a better candidate. Adding a 74HCT139 dual 1 to 4 decoder should do the trick, to decode 4 pairs of CS1/CS3 lines.



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