Tetroid interfaces hardware info

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Nasta
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Re: Tetroid interfaces hardware info

Postby Nasta » Sun Sep 03, 2017 12:05 am

tetroid wrote:
Nasta wrote:
Eh, I was hoping you had the 2V4 equations - the circuit seems a bit odd and I was looking forward to figuring out how it works :)





2V4 PAL16L8 euations


Thanks! Seems like an interesting way to do DRAM timing...

BTW did you implement internal RAM shadowing on your interface, since you do have the full 1M of SRAM on board?


tetroid
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Re: Tetroid interfaces hardware info

Postby tetroid » Sun Sep 03, 2017 5:57 pm

No, used only 768Kb of 1Mb.
I can add this memory, If anybody will advise the way to inplementing additional 256K into QL memory map, supporting by software.


Nasta
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Re: Tetroid interfaces hardware info

Postby Nasta » Sun Sep 03, 2017 6:03 pm

tetroid wrote:No, used only 768Kb of 1Mb.
I can add this memory, If anybody will advise the way to inplementing additional 256K into QL memory map, supporting by software.

As far as I am aware, even the old OS versions support 2M of RAM but the CPU does not have the required size of the address map (1M total).
For which addresses are your RAMs selected? I am assuming RAM1 is the usual 512k expansion (A19,18= 0,1 or 1,0), and RAM2 is the extra 256k (A19,18=1,1).


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Re: Tetroid interfaces hardware info

Postby martyn_hill » Sun Sep 03, 2017 6:42 pm

Hi Tedroid

The one modification that could add value and use some (though not all) of the spare 256KB SRAM - and would require NO software adjustment - is the shadowing of the first 128KB of standard QL memory. Its pretty trivial to accomplish and results in WRiting to both SRAM and internal 128KB (at the usual, contended bus data-rate), but ReaDing from the shadowed SRAM (disabling the ZX8301 via DSMCL) and resulting in faster read performance.

A nice feature for the next version...


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Re: Tetroid interfaces hardware info

Postby Dave » Sun Sep 03, 2017 6:55 pm

Where's a like button when you want one?


tetroid
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Re: Tetroid interfaces hardware info

Postby tetroid » Sun Sep 03, 2017 8:26 pm

Nasta wrote:
tetroid wrote:No, used only 768Kb of 1Mb.
I can add this memory, If anybody will advise the way to inplementing additional 256K into QL memory map, supporting by software.

As far as I am aware, even the old OS versions support 2M of RAM but the CPU does not have the required size of the address map (1M total).
For which addresses are your RAMs selected? I am assuming RAM1 is the usual 512k expansion (A19,18= 0,1 or 1,0), and RAM2 is the extra 256k (A19,18=1,1).


RAM1 - 256K only ( A19=0, A18=1 )
RAM2 - A19=1

I can change to any variants, if needed.


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Re: Tetroid interfaces hardware info

Postby tetroid » Sun Sep 03, 2017 8:26 pm

martyn_hill wrote:Hi Tedroid

The one modification that could add value and use some (though not all) of the spare 256KB SRAM - and would require NO software adjustment - is the shadowing of the first 128KB of standard QL memory. Its pretty trivial to accomplish and results in WRiting to both SRAM and internal 128KB (at the usual, contended bus data-rate), but ReaDing from the shadowed SRAM (disabling the ZX8301 via DSMCL) and resulting in faster read performance.

A nice feature for the next version...


Very interesting idea.


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Re: Tetroid interfaces hardware info

Postby martyn_hill » Sun Sep 03, 2017 9:06 pm

Just to add a bit of context (which you can find in a separate thread on the forum somewhere), I designed and built an internal expansion board for the QL previously that used a single 512KB SRAM IC, a GAL and a 3.6V backup-battery (plus some other less relevant parts).

The GAL partitions the address space in to the first 64KB of SRAM (shadowed and WR contended/RD uncontended) and a further 64KB (fully uncontended) but still shadowed -
both within the first 128KB of QL RAM address space.

Here, 'contended' involves allowing the ZX8301 to generate DTACKL, whereas 'uncontended' involves disabling DSMCL and generating DTACKL ourselves.

The next 256KB of SRAM is mapped as uncontended expansion RAM in the usual way, immediately above the standard 128KB RAM space.

The final 128KB of SRAM is mapped to the top 128KB of the standard 1MB QL memory map and implemented as non-volatile SRAM - to house my toolkits and other stuff between sessions. I used the Hermes Port2.6 (pin 37 - the defunct Microdrive WP line) as an output to gate the WR enable to the SRAM in that final 128KB, thus providing a write-protect mechanism (defaulted to protected at power-up).

Works quite nicely and, aside from the Hermes IPC replacement (plus its supporting tooklit/IPCEXT command), required no software/OS changes to give me 384 KB RAM, plus the 128KB non-volatile (EPROM-like), protected area, with faster RD access within the shadowed RAM area (about 15% faster, IIRC.)


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Re: Tetroid interfaces hardware info

Postby Nasta » Sun Sep 03, 2017 10:13 pm

Here is a table to explain how to do it:
A19 A18 A17 A16 RDWL /DTACKL /DSMCL /CSRAM1 /CSRAM0
--------------------------------------------------------------------------------
1 X X X X =DSL H L H
0 1 X X X =DSL H H L
0 0 1 1 X =DSL H H L
0 0 1 0 R =DSL H H L
0 0 1 0 W H* L H L

* Here data is written both to SRAM and 8301 RAM (CSRAM0=0, and DSMCL=0) but because 8301 is slower it is left to it to generate DTACKL, so DTACKL from your CPLD must be high.
This example supports both screen areas. If you have a free jumper to use, you can select to shadow only SCR0 (A15=0 only) and replace SCR1 with fast SRAM (DTACKL=DSL, DSMCL=H, CSRAM0=L)

EDIT: the forum software does not let me do formatting :(


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Re: Tetroid interfaces hardware info

Postby XorA » Sun Sep 03, 2017 10:28 pm

Nasta wrote:Here is a table to explain how to do it:
A19 A18 A17 A16 RDWL /DTACKL /DSMCL /CSRAM1 /CSRAM0
--------------------------------------------------------------------------------
1 X X X X =DSL H L H
0 1 X X X =DSL H H L
0 0 1 1 X =DSL H H L
0 0 1 0 R =DSL H H L
0 0 1 0 W H* L H L

* Here data is written both to SRAM and 8301 RAM (CSRAM0=0, and DSMCL=0) but because 8301 is slower it is left to it to generate DTACKL, so DTACKL from your CPLD must be high.
This example supports both screen areas. If you have a free jumper to use, you can select to shadow only SCR0 (A15=0 only) and replace SCR1 with fast SRAM (DTACKL=DSL, DSMCL=H, CSRAM0=L)

EDIT: the forum software does not let me do formatting :(


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Code: Select all

A19 A18 A17 A16 RDWL    /DTACKL /DSMCL /CSRAM1 /CSRAM0
------------------------------------------------------
 1   X   X   X   X       =DSL    H      L       H
 0   1   X   X   X       =DSL    H      H       L
 0   0   1   1   X       =DSL    H      H       L
 0   0   1   0   R       =DSL    H      H       L
 0   0   1   0   W        H*     L      H       L
 



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