Discussion about connecting RASPI to QL

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Nasta
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Re: Discussion about connecting RASPI to QL

Postby Nasta » Mon Jun 12, 2017 2:32 am

Welll.... for what it's worth, buffers should not be enabled towards the QL pins unless QL bus BGL is low (which would be the response of driving BRL low, this is the only pin on the bus you can do this to - of course interrupts etc do not count). Otherwise attempting to write something to the bus while the CPU is using it will result in bus contention and a crash. Reading the states of the pins is of course always OK. Leaving BGL low too long (milliseconds) will also corrupt data in some expansion RAM cards.
This would not be the route I'd take as it requires signal tracing or generating capability in the precision range of 100nS or less from the RasPI, and I have doubts it can be done while running any kind of OS on the RasPI.
But then, why not - if someone want's to push the PI to the limit, more power to them.


Derek_Stewart
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Re: Discussion about connecting RASPI to QL

Postby Derek_Stewart » Mon Jun 12, 2017 11:10 am

Hi,

Is it possible to redirect the QL video signal to use he HDMI display of the Raspberry PI?

The Acorn use of the Raspberry PI on their Tube Interface has a custom operating system running. So maybe this will have to be written as well for the QL.

Sounds too hard...


Regards,

Derek
Nasta
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Re: Discussion about connecting RASPI to QL

Postby Nasta » Mon Jun 12, 2017 4:37 pm

Sure, you 'just' write a completely new con/scr device, update wman and ptrgen, so that the QL 'only' handles standard OS calls and communicates them over to the Pi which actually does the work. So that's the theory. I'll let Marcel or someone explain the (im)practicalities of that much work (after he stops laughing :P ).

The thing with comparisons is, one needs to make sure to compare apples with apples. Acorn forced a strict adherence to their OS programming model and access to everything through OS calls, for which (amongst other things) the Tube interface was constructed.
Just to illustrate that this is not a question of 'adding a few buffers to the GPIO pins', the TUbe interface is a whole ULA chip with various FIFO buffers, which was developed right from the start at no small cost.

Is it possible to do something like this on the QL? Yes, of course - either using dual port RAM, od FIFO chips or implementing it in a FPGA. This is not trivial but it's the mall part of the problem. Writing the drivers is the large part, and that includes coding on both sides.

There are several intermediate solutions that could be made with far less investment. For instance, one could use a set of FIFOs to track write accesses to an area in RAM, or implement dual ported RAM, then patch eg. the Aurora driver to write there as if it were screen RAM. Every access gets pushed into the FIFO (address, data), and on the other side, it is emptied by the PI, and used to maintain it's own copy of the screen, which it can then display (perhaps even applying effects such as re-scaling to a different resolution, or displaying it in a window). Something much simpler but similar has been done before and it's called the QXL... As far as I remember, the SMSQ/E source for QXL is public, and it should provide a lot of clues on how this could be done.


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Re: Discussion about connecting RASPI to QL

Postby Dave » Mon Jun 12, 2017 11:44 pm

That is true if you want to do anything beyond the existing mode 4 and 8. If you stay within what the QL is natively doing and just 'somehow' export that data....

I did some personal experimenting over the weekend. I used my Pi 3. The Pi can keep up with monitoring the QL bus with two GPIOS, but if you add in two more GPIOs it starts to get marginal. Five GPIOs and it doesn't keep up. I didn't optimize what I was doing, but it was quite lean C.

However, there is a port on the Pi that has two serial lanes that can run at up to 800 Mbps each, for a combined 1.6 Gbps . This is the MIP CSI-2 connector, or camera connector. It's 1.2V, so some voltage translation will be needed ;) It can be clocked at any speed up to the limit, and the spec recommends you use the lowest clock possible. It supports RGB, RAW, YUV, or programmer defined.

Again, drivers would be needed. The technical barriers of meeting the MIPI-CSI-2 spec are pretty tough. But that is the only practical way to get video into the Pi.


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Re: Discussion about connecting RASPI to QL

Postby XorA » Tue Jun 13, 2017 8:54 am

Dave wrote:I did some personal experimenting over the weekend. I used my Pi 3. The Pi can keep up with monitoring the QL bus with two GPIOS, but if you add in two more GPIOs it starts to get marginal. Five GPIOs and it doesn't keep up. I didn't optimize what I was doing, but it was quite lean C.


Going to guess like most ARM SoCs GPIOs are banked in registers so the speed cost of 1-8 or 1-16 is the same. But you would need kernel driver to access like this on older kernel. On new kernels you can use /dev/gpio instead of /sys/gpio.

Graeme


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Re: Discussion about connecting RASPI to QL

Postby northernbob » Fri Nov 24, 2017 1:05 pm

ello there!

hows this little project going?

Over at the spec next community we are about to get our boards arrive(due weds) and so we are very interested in working on using the pizero as an accelerator.

Maybe we can compare notes?

If you wanna come say hello, we have a grp going atmo...

https://www.facebook.com/groups/772267459595751/

I did highlight this thread in the grp, also...


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Pr0f
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Re: Discussion about connecting RASPI to QL

Postby Pr0f » Fri Nov 24, 2017 2:09 pm

Would it make more sense for the Pi to simply produce a video display by decoding some RAM attached to it, and that RAM be written to instead of or as well as the internal RAM of the QL - like dual ported RAM, but the pi can then take the memory and produce hdmi output from it's own driver? To the QL this is simply a memory shadow of the existing memory so nothing needs to be done on the QL side. The pi would have to do the heavy lifting of translating the video data into something that makes sense from the Linux side...


Nasta
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Re: Discussion about connecting RASPI to QL

Postby Nasta » Fri Nov 24, 2017 9:48 pm

Pr0f wrote:Would it make more sense for the Pi to simply produce a video display by decoding some RAM attached to it, and that RAM be written to instead of or as well as the internal RAM of the QL - like dual ported RAM, but the pi can then take the memory and produce hdmi output from it's own driver? To the QL this is simply a memory shadow of the existing memory so nothing needs to be done on the QL side. The pi would have to do the heavy lifting of translating the video data into something that makes sense from the Linux side...


Short answer, YES.
And this is one way to do it efficiently. The only thing is, DPRAM is quite expensive. I mentioned it one of my posts above.


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Pr0f
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Re: Discussion about connecting RASPI to QL

Postby Pr0f » Fri Nov 24, 2017 10:03 pm

Nasta wrote:
Pr0f wrote:Would it make more sense for the Pi to simply produce a video display by decoding some RAM attached to it, and that RAM be written to instead of or as well as the internal RAM of the QL - like dual ported RAM, but the pi can then take the memory and produce hdmi output from it's own driver? To the QL this is simply a memory shadow of the existing memory so nothing needs to be done on the QL side. The pi would have to do the heavy lifting of translating the video data into something that makes sense from the Linux side...


Short answer, YES.
And this is one way to do it efficiently. The only thing is, DPRAM is quite expensive. I mentioned it one of my posts above.



Some FPGA's now sport quite a lot of on board RAM - maybe even enough to map out 64K of QL screen for dual screen support, and being on chip should be quite fast enough... The Lattice ICE range for instance...


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Re: Discussion about connecting RASPI to QL

Postby northernbob » Wed Nov 29, 2017 11:33 am

is none here monitoring how the next project is going? surely this has a influence on the future of the QL ?



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