The Sinclair QL Forum

Some sort of Maths accelerator comes to mind...

Might be an interesting exercise to produce a new 16 bit design of the aurora with 16 bit wide data path's and a 16 bit x 256K Dual ported VRAM - some of these RAM chips are quite sophisticated and offer settable start and end points for the serial access port - which is 16 bit's wide as well - givi...

Might be an interesting exercise to produce a new 16 bit design of the aurora with 16 bit wide data path's and a 16 bit x 256K Dual ported VRAM - some of these RAM chips are quite sophisticated and offer settable start and end points for the serial access port - which is 16 bit's wide as well - givi...

No - not yet - I have the circuit and parts to do this with the hi-lo programmer - but I haven't built that yet. I have the spare MAC that I got from you Derek, which is in the Aurora now. It looks like the timing is working ok - as I have stable video and it can take text from the SGC. It's quite a...

So last nights testing - Unplugged the QUBIDE card - and the display text is now readable. However, I still have some 'snow' on the screen which looks regular and indicates a probable address line issue. After some further research and looking at Marcels notes on the Gold Card boot - it seems the SG...

Yes - my plan was to dial it back in stages - to bring the machine back to the most basic setup. Question - will the QL boot without an IPC installed? This is custom case - so without the Superhermes - I have no keyboard at all. It's also clear that it must be booting as far as the patching process ...

So at the end of a long haul and not expecting a victory on the first power up I got a somewhat garbled screen I suspect it could be a number of things - as I have the following build: Aurora - not new and repaired with replacement of the largest logic device, the 'MAC' CPLD. ROM is a Minerva 1.98 i...

Excellent work - love the little screen too!

That's not good news Leon - you were making some excellent progress. Still, hopefully it's easily fixable. This is an excellent project.

The other approach is to control the clock going to the CPU - you can use a flip/flop or two within the FPGA to gate the clock signal to the CPU such that you get a 'glitchless' clock change - then you can select between a fast and slow clock. Any access to the ZX8302 can slow the CPU clock down if ...