The Sinclair QL Forum

Derek_Stewart wrote: ↑Fri May 31, 2024 8:18 pm Can the QL Rom Port lines used for interfacing?

Interface to what?

t0nyt wrote: ↑Fri May 31, 2024 6:45 pm Could I ask if this case fits a QIMSI Gold with Realtime Clock option please?

Unfortunately not. There is space on top where it is useless, but not on the bottom where the clock would sit.
You might want to contact QLobi, he is often willing to do changes.

Is it really the case that it can be used without the QL, as mentioned by PrOF? Yes, but I do not promote it. Because 80% of my work went into the QL specific connectivity and features. ;) If not connected to the QL, it can be powered from a 5V micro-USB adapter through the mouse port. I used the 3...

Back on topic: Probably the smallest cased QL compatible at the moment 56 x 38 mm

Many thanks. I have uploaded an update to the User Manual in my original post, so it is easier to find.

QIMSI Gold does not provide HDMI. As stated in the manual, it just has four two-lane LVDS outputs for connection to digital monitors.

qbits wrote: ↑Tue May 21, 2024 6:24 pm Do I have problem connecting a qmsi to my Monitor.

I don't think you'll have a problem. Just use a MIniHDMI to HDMI cable

Special thanks to organiser Detlef, to Urs for the history lesson and to Peter for the way forward and his last minute update of my Q68, despite some uncooperative Chinese hardware. Hi Bob, I hope your Q68 continued to work. That Chinese JTAG adaptor is in the recycling bin now. At home I have the ...

Hi Prof, many thanks for coming, it was a great meeting! I think it is realistic that most of us would come again next year. • Could or do any of Peter’s current line of FPGA based offerings support a letter box style LCD panel of 400 x 1280 / 1920? Ideally, the panel would allow a VGA or HDMI input...

I may f wasted money on the Tang Nano 20K, but at the time the idea of learning Verilog seemed a good idea. Maybe the Lattice approach might of been a better idea. Hi Derek, please do not get me wrong. Nothing speaks against the GoWin chip to learn Verilog. My question was more about the advantage ...