Search found 143 matches

by Nasta
Fri Apr 28, 2017 11:29 pm
Forum: Hardware
Topic: Q68 compatible peripherals on other QL systems
Replies: 25
Views: 883

Re: Q68 compatible peripherals on other QL systems

The only slight snag is for cases where successive bytes are transferred from a 'memory mapped' buffer, byte accesses with a 4 byte address shift will be needed. Thank goodness for LEA 4(An),An :P May I propose the following: Keep $18000..$1BFFF for byte mapped devices (so the IO hardware expects to...
by Nasta
Sat Apr 22, 2017 12:57 am
Forum: Hardware
Topic: Announcement - new QL Interface
Replies: 158
Views: 8862

Re: Announcement - new QL Interface

Also note that the shadowed/non shadowed results depend on the speed of access to the various OS tables and SuperBasic structures which may (on a normal system) reside in screen 1, which is still slow on writes. That being said, with the scroll test, and regular 68008CPU, it will be a very minor dif...
by Nasta
Mon Apr 17, 2017 1:31 am
Forum: Hardware
Topic: STOP instruction and DRAM refresh
Replies: 7
Views: 478

Re: STOP instruction and DRAM refresh

Heh, it is easy to forget that even digital is 'analog' and where the two meet, if one is not careful, trouble is guaranteed. With both DAC and ADC chips, it must be carefully considered what the analog and digital supplies are. Strangely enough, some chips (not to mention datasheets) have odd notio...
by Nasta
Sun Apr 16, 2017 9:40 am
Forum: Hardware
Topic: STOP instruction and DRAM refresh
Replies: 7
Views: 478

Re: STOP instruction and DRAM refresh

Yes, I understand that, it's a common problem. But I am not sure you understood the hardware technique to get around it in order not to stop the CPU completely while controlling the DACs. Double buffering means putting a register (usually something like a 74HC273) in front of the DAC data lines (unl...
by Nasta
Sat Apr 15, 2017 11:44 pm
Forum: Hardware
Topic: Fun things to do with an MC68EC020....
Replies: 153
Views: 16085

Re: Fun things to do with an MC68EC020....

1) The widest (data bus width) organization gives the least loads on the various buses. Keep in mind that all address lines on all SRAM chips are in parallel, but NOT the data lines - data lines go one per chip pair. 2) A 68020 access cycle takes 3 clocks of which approximately 2 are actually active...
by Nasta
Fri Apr 14, 2017 12:24 am
Forum: Hardware
Topic: Announcement - new QL Interface
Replies: 158
Views: 8862

Re: Announcement - new QL Interface

Minerva scans for ROMs at $0C000, $10000, $14000 and then from top of established RAM (as set by SV_RAMT) So, Minerva will only find TC at $10000, and never at $C0000. But end result is same :-) Yep. Minerva does the ROM scan a bit different from the original ROMS - and happily hits it as well. It ...
by Nasta
Fri Apr 14, 2017 12:14 am
Forum: Hardware
Topic: STOP instruction and DRAM refresh
Replies: 7
Views: 478

Re: STOP instruction and DRAM refresh

I'm sorry to say the way yo were doing the DAC write would be considered bas system design. The correct way is to use double-buffering. I.e. the interrupt source (timer) actually writes the previous sample from a buffer register into the DAC (so no latency) and then expects the CPU to re-fill the bu...
by Nasta
Mon Apr 10, 2017 10:39 pm
Forum: Hardware
Topic: Announcement - new QL Interface
Replies: 158
Views: 8862

Re: Announcement - new QL Interface

Forget paging on a multitasking system that requires position independent and re-entrant code. Nightmare to do, and completely incompatible with any QDOS/SMSQ/Minerva philosophy you care to name. But here is how you can put some of that RAM to good use: replace and shadow the original RAM, it will m...
by Nasta
Fri Apr 07, 2017 11:14 pm
Forum: Hardware
Topic: Machine detection by hardware
Replies: 13
Views: 832

Re: Machine detection by hardware

Something like this was already done by Minerva I think, regarding the GC and SGC - there it's done by looking for ASCII 'GOLD' at a certain address in the GC/SGC ROM. I suppose the idea is to identify the basic machine. This could be done by a flag (OK, a bit more, like a long word :) ) in the ROM ...
by Nasta
Thu Apr 06, 2017 1:11 am
Forum: Hardware
Topic: Machine detection by hardware
Replies: 13
Views: 832

Re: Machine detection by hardware

Someone has done work along these lines (detecting the CPU type, which is half of the work you need) but it relies heavily on trapoping the unimplemented instruction vector...
See here:
http://romanworkshop.blutu.pl/asm68/proc.htm

What does Minerva do to initialize the 68020 CPU correctly?

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