Search found 184 matches

by Nasta
Fri Oct 20, 2017 4:12 pm
Forum: Hardware
Topic: Qubbide Extended drives
Replies: 3
Views: 298

Re: Qubbide Extended drives

Yes exactly. In the case of the original QUBIDE, if I remember correctly, IOR/IOW is gated by DSL. Adding a decoder may produce too much of a delay. CS1/CS3 are only generated from address lines, so this is a better candidate. Adding a 74HCT139 dual 1 to 4 decoder should do the trick, to decode 4 pa...
by Nasta
Thu Oct 19, 2017 11:23 pm
Forum: Hardware
Topic: Qubbide Extended drives
Replies: 3
Views: 298

Re: Qubbide Extended drives

No, IDE bus signals CS1/CS3 or IOR/IOW are further decoded, generating up to 16 pairs of signals, one for each master/slave drive combination. Each pair of signals is decoded based on the state of address lines A4..A7, independent of anything else. The rest of the IDE signals are shared between all ...
by Nasta
Thu Oct 19, 2017 11:15 pm
Forum: Hardware
Topic: Qubata Syquest
Replies: 2
Views: 201

Re: Qubata Syquest

There must be a cartridge inside the drive for the software to recognize it as a hard disc.
by Nasta
Tue Sep 26, 2017 12:49 am
Forum: Hardware
Topic: QL ROM switcher
Replies: 15
Views: 856

Re: QL ROM switcher

Sadly, no... On the QL the ROMOEH line that selects the ROM is only generated for read cycles, and writes are necessary for programming the Flash chip in-circuit. Even worse, if a GC or SGC is used, the board does not even generate write cycles on the bus when addressing these addresses :( I maybe ...
by Nasta
Mon Sep 25, 2017 3:52 pm
Forum: Hardware
Topic: QL ROM switcher
Replies: 15
Views: 856

Re: QL ROM switcher

Sadly, no...
On the QL the ROMOEH line that selects the ROM is only generated for read cycles, and writes are necessary for programming the Flash chip in-circuit.
Even worse, if a GC or SGC is used, the board does not even generate write cycles on the bus when addressing these addresses :(
by Nasta
Wed Sep 13, 2017 7:38 pm
Forum: Hardware
Topic: ULA ZX8301 - TV Picture Capabilities
Replies: 44
Views: 4146

Re: ULA ZX8301 - TV Picture Capabilities

Putting a resistor in parallel with any other resistor results in a resistance value which is ALWAYS LESS than either of the two in parallel. So in this case you might try it with R86.
by Nasta
Wed Sep 13, 2017 11:22 am
Forum: Hardware
Topic: ULA ZX8301 - TV Picture Capabilities
Replies: 44
Views: 4146

Re: ULA ZX8301 - TV Picture Capabilities

Hi Nasta, Thank you, I was hoping for and awaiting your comment, too :-) Now again studying `QL Service Manual' and Issue#6 diagram. It says composite PAL signal is output/divided to UHF Modulator, capturing in the picture, when you say lowering amplitude, you mean changing values of the resistors ...
by Nasta
Tue Sep 12, 2017 10:54 pm
Forum: Hardware
Topic: ULA ZX8301 - TV Picture Capabilities
Replies: 44
Views: 4146

Re: ULA ZX8301 - TV Picture Capabilities

Before the next post becomes 'help, my QL stopped working!': 8301 PCENL decoding has nothing whatsoever to do with the RGB output. It's not 8301 decoding that is handled by the HAL but 8302, and that chip has nothing to do with the video. There are more subtle and not subtle differences in pre-HAL a...
by Nasta
Thu Sep 07, 2017 1:42 pm
Forum: Hardware
Topic: Tetroid interfaces hardware info
Replies: 31
Views: 1998

Re: Tetroid interfaces hardware info

It's a pity the original design equations are not available, as they could be re-targetted to a different CPLD. It is possible to reverse-engineer the JEDEC but it is a truly tedious job assuming the jedec fuse map of the CPLD is available (and it's not a given that it is, some manufacturers never p...
by Nasta
Sun Sep 03, 2017 10:13 pm
Forum: Hardware
Topic: Tetroid interfaces hardware info
Replies: 31
Views: 1998

Re: Tetroid interfaces hardware info

Here is a table to explain how to do it: A19 A18 A17 A16 RDWL /DTACKL /DSMCL /CSRAM1 /CSRAM0 -------------------------------------------------------------------------------- 1 X X X X =DSL H L H 0 1 X X X =DSL H H L 0 0 1 1 X =DSL H H L 0 0 1 0 R =DSL H H L 0 0 1 0 W H* L H L * Here data is written ...

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